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產(chǎn)品型號HY29LV320T的Datasheet PDF文件預(yù)覽

HY29LV320  
32 Mbit (2M x 16) Low Voltage Flash Memory  
KEY FEATURES  
n Single Power Supply Operation  
n Compatible With JEDEC standards  
– Read, program and erase operations from  
2.7 to 3.6 volts  
– Ideal for battery-powered applications  
n High Performance  
– 70, 80, 90 and 120 ns access time  
versions for full voltage range operation  
n Ultra-low Power Consumption (Typical/  
Maximum Values)  
Pinout and software compatible with  
single-power supply Flash devices  
Superior inadvertent write protection  
n Data# Polling and Toggle Bits  
Provide software confirmation of  
completion of program and erase  
operations  
n Ready/Busy (RY/BY#) Pin  
– Automatic sleep/standby current: 0.5/5.0  
μA  
Provides hardware confirmation of  
completion of program and erase  
operations  
– Read current: 9/16 mA (@ 5 MHz)  
– Program/erase current: 20/30 mA  
n Top and Bottom Boot Block Versions  
– Provide one 8 KW, two 4 KW, one 16 KW  
and sixty-three 32 KW sectors  
n Write Protect Function (WP#/ACC pin)  
? Allows hardware protection of the first or  
last 32 KW of the array, regardless of sector  
protect status  
n Secured Sector  
n Acceleration Function (WP#/ACC pin)  
? Provides accelerated program times  
n Erase Suspend/Erase Resume  
Suspends an erase operation to allow  
reading data from, or programming data  
to, a sector that is not being erased  
Erase Resume can then be invoked to  
complete suspended erasure  
– An extra 128-word, factory-lockable  
sector available for an Electronic Serial  
Number and/or additional secured data  
n Sector Protection  
– Allows locking of a sector or sectors to  
prevent program or erase operations  
within that sector  
– Temporary Sector Unprotect allows  
changes in locked sectors  
n Hardware Reset Pin (RESET#) Resets the  
Device to Reading Array Data  
n Fast Program and Erase Times (typicals)  
– Sector erase time: 0.5 sec per sector  
– Chip erase time: 32 sec  
n Space Efficient Packaging  
48-pin TSOP and 63-ball FBGA packages  
– Word program time: 11 μs  
LOGIC DIAGRAM  
– Accelerated program time per word: 7 μs  
n Automatic Erase Algorithm Preprograms  
and Erases Any Combination of Sectors  
or the Entire Chip  
n Automatic Program Algorithm Writes and  
Verifies Data at Specified Addresses  
n Compliant With Common Flash Memory  
Interface (CFI) Specification  
21  
16  
A[20:0]  
CE#  
DQ[15:0]  
– Flash device parameters stored directly  
on the device  
– Allows software driver to identify and use a  
variety of current and future Flash products  
n Minimum 100,000 Write Cycles per Sector  
WP#/ACC  
RY/BY#  
OE#  
W E #  
RESET#  
Revision 1.3, May 2002  
HY29LV320  
GENERAL DESCRIPTION  
The HY29LV320 is a 32 Mbit, 3 volt-only CMOS  
Flash memory organized as 2,097,152 (2M) words.  
The device is available in 48-pin TSOP and 63-  
ball FBGA packages. Word-wide data (x16) ap-  
pears on DQ[15:0].  
of other sectors. Device erasure is initiated by  
executing the Erase Command sequence. This  
initiates an internal algorithm that automatically  
preprograms the array (if it is not already pro-  
grammed) before executing the erase operation.  
As during programming cycles, the device auto-  
matically times the erase pulse widths and veri-  
fies proper cell margin. Sectors are arranged into  
designated groups for purposes of protection and  
unprotection. Sector Group Protection optionally  
disables both program and erase operations in any  
combination of the sector groups of the memory  
array, while Temporary Sector Group Unprotect  
allows in-system erasure and code changes in  
previously protected sector groups. Erase Sus-  
pend enables the user to put erase on hold for  
any period of time to read data from, or program  
data to, any sector that is not selected for era-  
sure. True background erase can thus be  
achieved. The device is fully erased when shipped  
from the factory.  
The HY29LV320 can be programmed and erased  
in-system with a single 3 volt VCC supply. Inter-  
nally generated and regulated voltages are pro-  
vided for program and erase operations, so that  
the device does not require a higher voltage VPP  
power supply to perform those functions. The de-  
vice can also be programmed in standard EPROM  
programmers. Access times as fast as 70ns over  
the full operating voltage range of 2.7 - 3.6 volts  
are offered for timing compatibility with the zero  
wait state requirements of high speed micropro-  
cessors. To eliminate bus contention, the  
HY29LV320 has separate chip enable (CE#), write  
enable (WE#) and output enable (OE#) controls.  
The device is compatible with the JEDEC single-  
power-supply Flash command set standard. Com-  
mands are written to the command register using  
standard microprocessor write timings, from where  
they are routed to an internal state-machine that  
controls the erase and programming circuits.  
Device programming is performed a word at a time  
by executing the four-cycle Program Command  
write sequence. This initiates an internal algorithm  
that automatically times the program pulse widths  
and verifies proper cell margin. Faster program-  
ming times are achieved by placing the  
HY29LV320 in the Unlock Bypass mode, which  
requires only two write cycles to program data in-  
stead of four.  
Addresses and data needed for the programming  
and erase operations are internally latched during  
write cycles, and the host system can detect  
completion of a program or erase operation by  
observing the RY/BY# pin, or by reading the DQ[7]  
(Data# Polling) and DQ[6] (Toggle) status bits.  
Hardware data protection measures include a low  
VCC detector that automatically inhibits write op-  
erations during power transitions.  
After a program or erase cycle has been com-  
pleted, or after assertion of the RESET# pin (which  
terminates any operation in progress), the device  
is ready to read data or to accept another com-  
mand. Reading data out of the device is similar to  
reading from other Flash or EPROM devices.  
The HY29LV320 features a sector architecture and  
is offered in two versions:  
The Secured Sector is an extra 128 word sector  
capable of being permanently locked at the fac-  
tory or by customers. The Secured Indicator Bit  
(accessed via the Electronic ID mode) is perma-  
nently set to a 1if the part is factory locked, and  
permanently set to a 0if customer lockable. This  
way, customer lockable parts can never be used  
to replace a factory locked part. Factory locked  
parts provide several options. The Secured Sec-  
tor may store a secure, random 8-word ESN (Elec-  
tronic Serial Number), customer code pro-  
grammed at the factory, or both. Customer Lock-  
n HY29LV320B - a device with boot-sector archi-  
tecture with the boot sectors at the bottom of the  
address range, containing one 8KW, two 4KW,  
one 16KW and sixty-three 32KW sectors.  
n HY29LV320T - a device with boot-sector archi-  
tecture with the boot sectors at the top of the  
address range, containing one 8KW, two 4KW,  
one 16KW and sixty-three 32KW sectors.  
The HY29LV320s sector erase architecture allows  
any number of array sectors to be erased and re-  
programmed without affecting the data contents  
r1.3/May 02  
2
HY29LV320  
able parts may utilize the Secured Sector as bo-  
nus space, reading and writing like any other Flash  
sector, or may permanently lock their own code  
there.  
Common Flash Memory Interface (CFI)  
To make Flash memories interchangeable and to  
encourage adoption of new Flash technologies,  
major Flash memory suppliers developed a flex-  
ible method of identifying Flash memory sizes and  
configurations in which all necessary Flash device  
parameters are stored directly on the device.  
Parameters stored include memory size, byte/word  
configuration, sector configuration, necessary volt-  
ages and timing information. This allows one set  
of software drivers to identify and use a variety of  
different, current and future Flash products. The  
standard which details the software interface nec-  
essary to access the device to identify it and to  
determine its characteristics is the Common Flash  
Memory Interface (CFI) Specification. The  
HY29LV320 is fully compliant with this specification.  
The WP#/ACC pin provides two functions. The  
Write Protect function provides a hardware method  
of protecting the boot sectors without using a high  
voltage. The Accelerate function speeds up pro-  
gramming operations, and is intended primarily to  
allow faster manufacturing throughput.  
Two power-saving features are embodied in the  
HY29LV320. When addresses have been stable  
for a specified amount of time, the device enters  
the automatic sleep mode. The host can also place  
the device into the standby mode. Power con-  
sumption is greatly reduced in both these modes.  
BLOCK DIAGRAM  
DQ[15:0]  
A[20:0]  
STATE  
CONTROL  
ERASE VOLTAGE  
GENERATOR AND  
SECTOR SWITCHES  
I/O BUFFERS  
DATA LATCH  
Y-GATING  
COMMAND  
REGISTER  
CFI  
CONTROL  
CFI DATA  
MEMORY  
WE#  
CE#  
I/O CONTROL  
OE#  
PROGRAM  
VOLTAGE  
GENERATOR  
RESET#  
RY/BY#  
WP#/ACC  
Y-DECODER  
X-DECODER  
32 Mb FLASH  
MEMORY  
ARRAY  
(67 Sectors)  
A[20:0]  
TIMER  
VC C  
DETECTOR  
128-word  
FLASH  
Security Sector  
r1.3/May 02  
3
HY29LV320  
SIGNAL DESCRIPTIONS  
Name  
Type  
Description  
Address, active High. These 21 inputs select one of 2,097,152 (2M) words  
within the array for read or write operations.  
A[20:0]  
Inputs  
Inputs/Outputs Data Bus, active High. These pins provide a 16-bit data path for read and  
DQ[15:0]  
CE#  
Tri-state  
write operations.  
Chip Enable, active Low. This input must be asserted to read data from or  
write data to the HY29LV320. When High, the data bus is tri-stated and the  
device is placed in the Standby mode.  
Input  
Output Enable, active Low. This input must be asserted for read operations  
and negated for write operations. When High, data outputs from the device are  
disabled and the data bus pins are placed in the high impedance state.  
OE#  
WE#  
Input  
Input  
Write Enable, active Low. Controls writing of commands or command  
sequences for various device operations. A write operation takes place when  
WE# is asserted while CE# is also Low and OE# is High.  
Hardware Reset, active Low. Provides a hardware method of resetting the  
HY29LV320 to the read array state. When the device is reset, it immediately  
terminates anyoperation in progress. The data bus is tri-stated and all read/write  
commands are ignored while the input is asserted. While RESET# is asserted  
the device will be in the Standby mode.  
RESET#  
RY/BY#  
Input  
Ready/Busy Status. Indicates whether a write or erase command is in  
progress or has been completed. Valid after the rising edge of the final WE#  
Open Drain pulse of a command sequence. Remains Low while the device is actively  
programming data or erasing, and goes High when it is ready to read array data.  
Output  
Write Protect, active Low/Accelerate (VHH).  
Placing this pin at VIL disables program and erase operations in the top or bottom  
32K words of the array. The affected sectors are sectors S0 - S3 for the  
HY29LV320B and sectors S63 - S66 for the HY29LV320T.  
If the pin is placed at VIH, the protection state of those two sectors reverts to  
whether they were last set to be protected or unprotected using the Sector Group  
Protection and Unprotection capability of the HY29LV320.  
If VHH is applied to this input, the device enters the Unlock Bypass mode,  
Input  
WP#/ACC  
temporarily unprotects any protected sectors, and uses the higher voltage on the  
pin to reduce the time required for program operations. (The system would then  
use the two-cycle program command sequence as required by the Unlock  
Bypass mode.) Removing VHH from the pin returns the device to normal  
operation.  
This pin must not be at VHH for operations other than accelerated programming,  
or device damage mayresult. Leaving the pin floating or unconnected mayresult  
in inconsistent device operation.  
High Input. Connect to VIH or to VCC to provide compatibility with similar x8/x16  
devices.  
VIH  
Input  
3-volt (nominal) power supply.  
Power and signal ground.  
VCC  
VSS  
--  
--  
r1.3/May 02  
4
HY29LV320  
PIN CONFIGURATIONS  
63-BallFBGA - Top View, Balls Facing Down  
L8  
A 8  
N C  
B 8  
N C  
M 8  
N C  
N C  
L7  
A 7  
N C  
B 7  
N C  
C 7  
D 7  
E7  
F7  
G 7  
H 7  
J7  
K7  
M 7  
N C  
A [13] A [12] A [14] A [15] A [16]  
V
D Q [15]  
V
N C  
IH  
SS  
C 6  
D 6  
E6  
F6  
G 6  
H 6  
J6  
K6  
A [9]  
A [8] A [10] A [11] D Q [7] D Q [14] D Q [13] D Q [6]  
C 5  
D 5  
E5  
N C  
F5  
G 5  
H 5  
J5  
K5  
W E# R ESET#  
A [19] D Q [5] D Q [12]  
V
D Q [4]  
C C  
C 4  
D 4  
E4  
F4  
G 4  
H 4  
J4  
K4  
W P#/ACC  
R Y /B Y #  
A [18] A [20] D Q [2] D Q [10] D Q [11] D Q [3]  
C 3  
D 3  
E3  
F3  
G 3  
H 3  
J3  
K3  
A [7] A [17] A [6]  
A [5] D Q [0] D Q [8] D Q [9] D Q [1]  
A 2  
N C  
C 2  
D 2  
E2  
F2  
G 2  
H 2  
J2  
K2  
L2  
M 2  
N C  
A [3]  
A [4]  
A [2]  
A [1]  
A [0]  
C E#  
O E#  
V
N C  
SS  
A 1  
N C  
B 1  
N C  
L1  
M 1  
N C  
N C  
A[15]  
A[14]  
A[13]  
A[12]  
A[11]  
A[10]  
A[9]  
1
2
3
4
5
6
7
48  
47  
46  
45  
44  
43  
42  
A[16]  
VIH  
VSS  
DQ[15]  
DQ[7]  
DQ[14]  
DQ[6]  
A[8]  
A[19]  
8
9
41  
40  
DQ[13]  
DQ[5]  
A[20]  
WE#  
10  
11  
39  
38  
DQ[12]  
DQ[4]  
RESET#  
NC  
12  
13  
37  
36  
VC C  
DQ[11]  
TSOP48  
WP#/ACC  
RY/BY#  
A[18]  
14  
15  
16  
17  
18  
19  
20  
35  
34  
33  
32  
31  
30  
29  
DQ[3]  
DQ[10]  
DQ[2]  
DQ[9]  
DQ[1]  
DQ[8]  
DQ[0]  
A[17]  
A[7]  
A[6]  
A[5]  
A[4]  
A[3]  
A[2]  
A[1]  
21  
22  
23  
24  
28  
27  
26  
25  
OE#  
VSS  
CE#  
A[0]  
r1.3/May 02  
5
HY29LV320  
CONVENTIONS  
Unless otherwise noted, a positive logic (active  
High) convention is assumed throughout this docu-  
ment, whereby the presence at a pin of a higher,  
more positive voltage (VIH) causes assertion of the  
signal. A #symbol following the signal name,  
e.g., RESET#, indicates that the signal is asserted  
in the Low state (VIL). See DC specifications for  
VIH and VIL values.  
Whenever a signal is separated into numbered  
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of  
bits may also be shown collectively, e.g., as  
DQ[7:0].  
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .  
. . , E, F) indicates a number expressed in hexadeci-  
mal notation. The designation 0bXXXX indicates a  
number expressed in binary notation (X = 0, 1).  
MEMORY ARRAY ORGANIZATION  
customer-lockable devices from being used to re-  
place devices that are factory locked. The bit pre-  
vents cloning of a factory locked part and thus  
ensures the security of the ESN once the product  
is shipped to the field.  
The system accesses the Sec2 through a com-  
mand sequence (see Enter/Exit Secured Sector  
Command Sequence). After the system has writ-  
ten the Enter Secured Sector command sequence,  
it may read the Sec2 by using the addresses speci-  
fied in Table 3. This mode of operation continues  
until the system issues the Exit Secured Sector  
command sequence, or until power is removed  
from the device. On power-up, or following a hard-  
ware reset, the device reverts to addressing the  
Flash array.  
The 32 Mbit Flash memory array is organized into  
67 blocks called sectors (S0, S1, . . . , S66). A  
sector or several contiguous sectors are defined  
as a sector group. A sector is the smallest unit  
that can be erased and a sector group is the small-  
est unit that can be protected to prevent acciden-  
tal or unauthorized erasure.  
In the HY29LV320, four of the sectors, which com-  
prise the boot block, are sized as follows: one of  
eight Kwords, two of four Kwords and one of  
sixteen Kwords. The remaining 63 sectors are  
sized at 32 Kwords. The boot block can be lo-  
cated at the bottom of the address range  
(HY29LV320B) or at the top of the address range  
(HY29LV320T).  
Tables 1 and 2 define the sector addresses and  
corresponding array address ranges for the top  
and bottom boot block versions of the HY29LV320.  
See Tables 6 and 7 for sector group definitions.  
Note: While in the Sec2 Read mode, only the reading of  
the Replaced Sector(Table 3) is affected. Accesses  
within the specified sector, but outside the address range  
specified in the table, may produce indeterminate results.  
Reading of all other sectors in the device continues nor-  
mally while in this mode.  
Secured Sector Flash Memory Region  
Sec2 Programmed and Protected At the Factory  
The Secured Sector (Sec2) feature provides a 128  
word Flash memory region that enables perma-  
nent part identification through an Electronic Se-  
rial Number (ESN). An associated Sec2 Indica-  
torbit, which is permanently set at the factory and  
cannot be changed, indicates whether or not the  
Sec2 is locked when shipped from the factory.  
The device is offered with the Sec2 either factory  
locked or customer lockable. The factory-locked  
version is always protected when shipped from  
the factory, and has the Sec2 Indicator bit perma-  
nently set to a 1. The customer-lockable version  
is shipped with the Sec2 unprotected, allowing  
customers to utilize the sector in any manner they  
choose, and has the Sec2 Indicator bit permanently  
set to a 0. Thus, the Sec2 Indicator bit prevents  
In a factory-locked device, the Sec2 is protected  
when the device is shipped from the factory and  
cannot be modified in any way. The device is avail-  
able preprogrammed with one of the following:  
n A random, secure ESN only  
n Customer code  
n Both a random, secure ESN and customer  
code  
In devices that have an ESN, it will be located at  
the bottom of the sector: starting at word address  
0x000000 and ending at 0x000007 for a Bottom  
Boot device, and starting at word address  
0x1FE000 and ending at 0x1FE007 for a Top Boot  
device. See Table 3.  
r1.3/May 02  
6
HY29LV320  
Table 1. HY29LV320T (Top Boot Block) Memory Array Organization  
Sector Address 1  
Sect-  
or (KWord)  
Size  
Address Range 2, 3  
A[20]  
A[19]  
A[18]  
A[17]  
A[16]  
A[15]  
A[14]  
A[13]  
A[12]  
S0  
S1  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x000000 - 0x007FFF  
0x008000 - 0x00FFFF  
0x010000 - 0x017FFF  
0x018000 - 0x01FFFF  
0x020000 - 0x027FFF  
0x028000 - 0x02FFFF  
0x030000 - 0x037FFF  
0x038000 - 0x03FFFF  
0x040000 - 0x047FFF  
0x048000 - 0x04FFFF  
0x050000 - 0x057FFF  
0x058000 - 0x05FFFF  
0x060000 - 0x067FFF  
0x068000 - 0x06FFFF  
0x070000 - 0x077FFF  
0x078000 - 0x07FFFF  
0x080000 - 0x087FFF  
0x088000 - 0x08FFFF  
0x090000 - 0x097FFF  
0x098000 - 0x09FFFF  
0x0A0000 - 0x0A7FFF  
0x0A8000 - 0x0AFFFF  
0x0B0000 - 0x0B7FFF  
0x0B8000 - 0x0BFFFF  
0x0C0000 - 0x0C7FFF  
0x0C8000 - 0x0CFFFF  
0x0D0000 - 0x0D7FFF  
0x0D8000 - 0x0DFFFF  
0x0E0000 - 0x0E7FFF  
0x0E8000 - 0x0EFFFF  
0x0F0000 - 0x0F7FFF  
0x0F8000 - 0x0FFFFF  
Same as S0 - S30  
S2  
S3  
S4  
S5  
S6  
S7  
S8  
S9  
S10  
S11  
S12  
S13  
S14  
S15  
S16  
S17  
S18  
S19  
S20  
S21  
S22  
S23  
S24  
S25  
S26  
S27  
S28  
S29  
S30  
S31  
S32 -  
S62  
S63  
S64  
S65  
S66  
32  
Same as S0 - S30 except A[20] = 1  
except MSD = 1  
16  
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
X
0
0
1
X
0
0x1F8000 - 0x1FBFFF  
0x1FC000 - 0x1FCFFF  
0x1FD000 - 0x1FDFFF  
0x1FE000 - 0x1FFFFF  
4
1
8
X
Notes:  
1. Xindicates dont care.  
2. 0xN. . . Nindicates an address in hexadecimal notation.  
3. The address range is A[20:0].  
r1.3/May 02  
7
HY29LV320  
Table 2. HY29LV320B (Bottom Boot Block) Memory Array Organization  
Sector Address 1  
Sect-  
or (KWord)  
Size  
Address Range 2, 3  
A[20]  
A[19]  
A[18]  
A[17]  
A[16]  
A[15]  
A[14]  
A[13]  
A[12]  
S0  
S1  
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
X
0
0x000000 - 0x001FFF  
0x002000 - 0x002FFF  
0x003000 - 0x003FFF  
0x004000 - 0x007FFF  
0x008000 - 0x00FFFF  
0x010000 - 0x017FFF  
0x018000 - 0x01FFFF  
0x020000 - 0x027FFF  
0x028000 - 0x02FFFF  
0x030000 - 0x037FFF  
0x038000 - 0x03FFFF  
0x040000 - 0x047FFF  
0x048000 - 0x04FFFF  
0x050000 - 0x057FFF  
0x058000 - 0x05FFFF  
0x060000 - 0x067FFF  
0x068000 - 0x06FFFF  
0x070000 - 0x077FFF  
0x078000 - 0x07FFFF  
0x080000 - 0x087FFF  
0x088000 - 0x08FFFF  
0x090000 - 0x097FFF  
0x098000 - 0x09FFFF  
0x0A0000 - 0x0A7FFF  
0x0A8000 - 0x0AFFFF  
0x0B0000 - 0x0B7FFF  
0x0B8000 - 0x0BFFFF  
0x0C0000 - 0x0C7FFF  
0x0C8000 - 0x0CFFFF  
0x0D0000 - 0x0D7FFF  
0x0D8000 - 0x0DFFFF  
0x0E0000 - 0x0E7FFF  
0x0E8000 - 0x0EFFFF  
0x0F0000 - 0x0F7FFF  
0x0F8000 - 0x0FFFFF  
0x100000 - 0x107FFF  
Same as S4 - S34  
except MSD = 1  
4
S2  
4
0
1
1
S3  
16  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S4  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S5  
S6  
S7  
S8  
S9  
S10  
S11  
S12  
S13  
S14  
S15  
S16  
S17  
S18  
S19  
S20  
S21  
S22  
S23  
S24  
S25  
S26  
S27  
S28  
S29  
S30  
S31  
S32  
S33  
S34  
S35  
S36 -  
S66  
32  
Same as S4 - S34 except A[20] = 1  
Notes:  
1. Xindicates dont care.  
2. 0xN. . . Nindicates an address in hexadecimal notation.  
3. The address range is A[20:0].  
r1.3/May 02  
8
HY29LV320  
Table 3. HY29LV320 Secure Sector Addressing  
Sector Size  
Electronic Serial Number  
Address Range 2  
Device  
Replaced Sector1  
Address Range 2  
(Words)  
HY29LV320T  
HY29LV320B  
128  
S66 (Table 1)  
S0 (Table 2)  
0x1FE000 - 0x1FE07F  
0x000000 - 0x00007F  
0x1FE000 - 0x1FE007  
0x000000 - 0x000007  
128  
Notes:  
1. Accesses within the specified sector, but outside the specified address range, may produce indeterminate results.  
2. 0xN. . . Nindicates an address in hexadecimal notation. The address range is A[20:0].  
Sec2 NOT Programmed or Protected at the Factory  
tection of the Secure Sector without raising any  
device pin to a high voltage. Note that this  
method is only applicable to the Secure Sector.  
be treated as an additional Flash memory space  
If the security feature is not required, the Sec2 can  
of 128 words. The Sec2 can be read, programmed,  
n Once the Secure Sector is locked and verified,  
and erased as often as required. The Sec2 area  
the system must write the Exit Secure Sector  
can be protected using the following procedure:  
command sequence to return to reading and  
writing the remainder of the array.  
n Write the three-cycle Enter Secure Sector Re-  
Sec2 protection must be used with caution since,  
once protected, there is no procedure available  
for unprotecting the Sec2 area and none of the  
bits in the Sec2 memory space can be modified in  
any way.  
gion command sequence.  
n Follow the in-system sector protect algorithm  
as shown in Figure 3, except that RESET# may  
be at either VIH or VID. This allows in-system pro-  
BUS OPERATIONS  
Device bus operations are initiated through the  
internal command register, which consists of sets  
of latches that store the commands, along with  
the address and data information, if any, needed  
to execute the specific command. The command  
register itself does not occupy any addressable  
memory location. The contents of the command  
register serve as inputs to an internal state ma-  
chine whose outputs control the operation of the  
device.  
the memory content occurs during the power tran-  
sition. No command is necessary in this mode to  
obtain array data, and the device remains enabled  
for read accesses until the command register con-  
tents are altered.  
This device features an Erase Suspend mode.  
While in this mode, the host may read the array  
data from any sector of memory that is not marked  
for erasure. If the host reads from an address  
within an erase-suspended (or erasing) sector, or  
while the device is performing a program opera-  
tion, the device outputs status data instead of ar-  
ray data. After completing an Automatic Program  
or Erase algorithm within a sector, that sector au-  
tomatically returns to the read array data mode.  
After completing a programming operation in the  
Erase Suspend mode, the system may once again  
read array data with the same exception noted  
above.  
Table 4 lists the normal bus operations, the inputs  
and control levels they require, and the resulting  
outputs. Certain bus operations require a high  
voltage on one or more device pins. Those are  
described in Table 5.  
Data is read from the HY29LV320 by using stan-  
dard microprocessor read cycles while placing the  
word address on the devices address inputs. The  
host system must drive the CE# and OE# pins  
LOW and drive WE# high for a valid read opera-  
tion to take place. See Figure 1.  
The host must issue a hardware reset or the soft-  
ware reset command to return a sector to the read  
array data mode if DQ[5] goes high during a pro-  
gram or erase cycle, or to return the device to the  
read array data mode while it is in the Electronic  
ID mode.  
The HY29LV320 is automatically set for reading  
array data after device power-up and after a hard-  
ware reset to ensure that no spurious alteration of  
r1.3/May 02  
9
HY29LV320  
Table 4. HY29LV320 Normal Bus Operations1  
Operation  
CE#  
OE# WE# RESET# WP#/ACC A[20:0]  
DQ[15:0]  
Read  
Write  
L
L
H
H
X
X
X
X
H
L
H
L/H  
Notes 2, 3  
L/H  
AIN  
AIN  
X
DOUT  
DIN  
L
H
Output Disable  
L
H
X
X
X
X
H
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
CE# Normal Standby  
CE# Deep Standby  
Hardware Reset (Normal Standby)  
Hardware Reset (Deep Standby)  
Notes:  
H
H
VCC ± 0.3V  
L
L/H  
X
VCC ± 0.3V  
L/H  
X
X
X
L/H  
X
V
SS ± 0.3V  
L/H  
X
1. L = VIL, H = VIH, X = Dont Care (L or H), DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.  
2. If WP#/ACC = VIL, the boot sectors are protected. If WP#/ACC = VIH, the protection state of the boot sectors depends on  
whether they were last protected or unprotected using the method described in Sector Group Protection and Unprotection.  
If WP#/ACC = VHH, all sectors will be unprotected.  
3. See Table 5 for Accelerated Program function with WP#/ACC = VHH  
.
Table 5. HY29LV320 Bus Operations Requiring High Voltage1, 2  
WP#/  
Operation  
CE# OE# WE# RESET#  
A[20:12]3 A[9] A[6] A[1] A[0] DQ[15:0]7  
ACC  
5
Accelerated Program  
Sector Group Protect  
Sector Unprotect  
L
L
L
H
H
H
L
L
L
H
VHH  
AIN  
SGA  
X
AIN  
X
AIN  
L
AIN  
H
AIN  
L
CMDIN  
CMDIN  
DIN  
VID  
VID  
H
H
X
H
H
L
Temporary Sector  
Unprotect  
Manufacturer Code  
HY29LV320B  
Device  
--  
L
L
--  
L
L
--  
H
H
VID  
H
Note 4  
L/H  
--  
X
X
--  
--  
L
L
--  
L
L
--  
L
--  
6
VID  
VID  
0x00AD  
0x227D  
0x227E  
H
L/H  
H
Code  
HY29LV320T  
Sector  
Protect  
State 4  
Unprotected  
0xXX00  
0xXX01  
L
L
L
L
H
H
H
H
L/H  
L/H  
SA  
X
VID  
VID  
L
L
H
H
L
Protected  
Factory  
Locked  
Not Factory  
Locked  
Secure  
Sector  
Indicator  
Bit  
0xXX80  
0xXX00  
H
Notes:  
1. L = VIL, H = VIH, X = Dont Care (L or H), VID = 12V nominal. See DC Characteristics for voltage specifications.  
2. Address bits not specified are Dont Care.  
3. SA = Sector Address, SGA = Sector Group Address. See Tables 1, 2, 6, and 7.  
4. If WP#/ACC = VIL, the boot sectors remain protected.  
AIN = address input.  
5. Protected sectors are temporarily unprotected when VHH is applied to the WP#/ACC pin.  
6. Normal read, write and output disable operations are used in this mode. See Table 4.  
7. DIN = input data, CMDIN = Command input.  
r1.3/May 02  
10  
HY29LV320  
OE#  
ADR  
CE#  
W E #  
W E #  
ADR  
CE#  
OE#  
tAH  
tDS  
DATA  
IN  
DATA  
OUT  
tAS  
tDH  
tACC  
tCE  
Figure 2. Write Operation  
tOE  
Note: WP# sector protection cannot be used while WP#/  
ACC = VHH. Thus, all sectors are unprotected and can  
be erased and programmed while in Accelerated Pro-  
gramming mode.  
Figure 1. Read Operation  
Write Operation  
Note: The Accelerate function does not affect the time  
Certain operations, including programming data  
and erasing sectors of memory, require the host  
to write a command or command sequence to the  
HY29LV320. Writes to the device are performed  
by placing the word address on the devices ad-  
dress inputs while the data to be written is input  
on DQ[15:0]. The host system must drive the CE#  
and WE# pins Low and drive OE# High for a valid  
write operation to take place. All addresses are  
latched on the falling edge of WE# or CE#, which-  
ever happens later. All data is latched on the ris-  
ing edge of WE# or CE#, whichever happens first.  
See Figure 2.  
required for Erase operations.  
See the description of the WP#/ACC pin in the  
Pin Descriptions table for additional information  
on this function.  
Write Protect Function  
The Write Protect function provides a hardware  
method of protecting the boot sectors without us-  
ing VID. This function is a second function pro-  
vided by the WP#/ACC pin.  
Placing this pin at VIL disables program and erase  
operations in the bottom or top 32K words of the  
array (the boot sectors). The affected sectors are  
as follows (see Tables 1 and 2):  
.The Device Commandssection of this specifi-  
cation provides details on the specific device com-  
mands implemented in the HY29LV320.  
n HY29LV320B: S0 S3  
n HY29LV320T: S63 S66  
Accelerated Program Operation  
If the pin is placed at VIH, the protection state of  
those sectors reverts to whether they were last  
set to be protected or unprotected using the  
method described in the Sector Group Protection  
and Unprotection sections.  
This device offers accelerated program operations  
through the Acceleratefunction provided by the  
WP#/ACC pin. This function is intended primarily  
for faster programming throughput at the factory.  
If VHH is applied to the WP#/ACC input, the device  
enters the Unlock Bypass mode, temporarily  
unprotects any protected sectors, and uses the  
higher voltage on the pin to reduce the time re-  
quired for program operations. The system would  
then use the two-cycle program command se-  
quence as required by the Unlock Bypass mode.  
Removing VHH from the pin returns the device to  
normal operation.  
Note: Sectors protected by WP#/ACC = VIL remain pro-  
tected during Temporary Sector Unprotect and cannot  
be erased or programmed. Also see note under Accel-  
erate Program Operation above.  
Standby Operation  
When the system is not reading or writing to the  
device, it can place the device in the Standby  
r1.3/May 02  
11  
HY29LV320  
bus pins, and ignores all read/write commands for  
the duration of the RESET# pulse. The device also  
resets the internal state machine to reading array  
data. If an operation was interrupted by the as-  
sertion of RESET#, it should be reinitiated once  
the device is ready to accept another command  
sequence to ensure data integrity.  
mode. In this mode, current consumption is greatly  
reduced, and the data bus outputs are placed in  
the high impedance state, independent of the OE#  
input. The Standby mode can invoked using two  
methods.  
The device enters the CE# Controlled Deep  
Standby mode when the CE# and RESET# pins  
are both held at VCC ± 0.3V. Note that this is a  
more restricted voltage range than VIH . If both  
CE# and RESET# are held at VIH , but not within  
VCC ± 0.3V, the device will be in the Normal Standby  
mode, but the standby current will be greater.  
Current is reduced for the duration of the RESET#  
pulse as described in the Standby Operation sec-  
tion.  
If RESET# is asserted during a program or erase  
operation (RY/BY# pin is Low), the RY/BY# pin  
remains Low (busy) until the internal reset opera-  
tion is complete, which requires a time of tREADY  
(during Automatic Algorithms). The system can  
thus monitor RY/BY# to determine when the reset  
operation completes, and can perform a read or  
write operation tRB after RY/BY# goes High. If  
RESET# is asserted when a program or erase  
operation is not executing (RY/BY# pin is High),  
the reset operation is completed within a time of  
tRP. In this case, the host can perform a read or  
write operation tRH after the RESET# pin returns  
High.  
Note: If the device is deselected during erasure or  
programming, it continues to draw active current until  
the operation is completed.  
The device enters the RESET# Controlled Deep  
Standby mode when the RESET# pin is held at  
VSS ± 0.3V. If RESET# is held at VIL but not within  
VSS ± 0.3V, the standby current will be greater. See  
RESET# section for additional information on the  
reset operation.  
The device requires standard access time (tCE)  
for read access when the device is in any of the  
standby modes before it is ready to read data.  
The RESET# pin may be tied to the system reset  
signal. Thus, a system reset would also reset the  
device, enabling the system to read the boot-up  
firmware from the Flash memory.  
Sleep Mode  
The sleep mode automatically minimizes device  
power consumption. This mode is automatically  
entered when addresses remain stable for tACC  
+
Sector Group Protect Operation  
30 ns (typical) and is independent of the state of  
the CE#, WE#, and OE# control signals. Standard  
address access timings provide new data when  
addresses are changed. While in sleep mode,  
output data is latched and always available to the  
system. The device does not enter sleep mode if  
an automatic program or automatic erase algo-  
rithm is in progress.  
The hardware sector group protection feature dis-  
ables both program and erase operations in any  
combination of sector groups. A sector group con-  
sists of a single sector or a group of adjacent sec-  
tors, as specified in Tables 6 and 7. This function  
can be implemented either in-system or by using  
programming equipment. It requires a high volt-  
age (VID) on the RESET# pin and uses standard  
microprocessor bus cycle timing to implement  
sector protection. The flow chart in Figure 3 illus-  
trates the algorithm.  
Output Disable Operation  
When the OE# input is at VIH , output data from  
the device is disabled and the data bus pins are  
placed in the high impedance state.  
The HY29LV320 is shipped with all sectors un-  
protected. It is possible to determine whether a  
sector is protected or unprotected. See the Elec-  
tronic ID Mode section for details.  
Reset Operation  
The RESET# pin provides a hardware method of  
resetting the device to reading array data. When  
the RESET# pin is driven low for the minimum  
specified period, the device immediately termi-  
nates any operation in progress, tri-states the data  
Sector Unprotect Operation  
The hardware sector unprotection feature re-en-  
ables both program and erase operations in pre-  
r1.3/May 02  
12  
HY29LV320  
Table 6. Sector Groups - Top Boot Version  
Table 7. Sector Groups - Bottom Boot Version  
Sectors  
(Table 1)  
Group Address Block Size  
Sectors  
(Table 2)  
Group Address Block Size  
Group  
Group  
A[20:12]  
(KWords)  
A[20:12]  
(KWords)  
SG0  
S0  
0 0 0 0 0 0 X X X  
0 0 0 0 0 1 X X X  
32  
SG0  
SG1  
SG2  
SG3  
S0  
S1  
S2  
S3  
0 0 0 0 0 0 0 0 X  
0 0 0 0 0 0 0 1 0  
0 0 0 0 0 0 0 1 1  
0 0 0 0 0 0 1 X X  
0 0 0 0 0 1 X X X  
8
4
4
SG1  
S1 - S3 0 0 0 0 1 0 X X X  
0 0 0 0 1 1 X X X  
S4 - S7 0 0 0 1 X X X X X  
S8 -S11 0 0 1 0 X X X X X  
96  
16  
SG2  
SG3  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
SG4  
SG5  
S4 - S6 0 0 0 0 1 0 X X X  
0 0 0 0 1 1 X X X  
S7 - S10 0 0 0 1 X X X X X  
96  
SG4 S12 - S15 0 0 1 1 X X X X X  
SG5 S16 - S19 0 1 0 0 X X X X X  
SG6 S20 - S23 0 1 0 1 X X X X X  
SG7 S24 - S27 0 1 1 0 X X X X X  
SG8 S28 - S31 0 1 1 1 X X X X X  
SG9 S32 - S35 1 0 0 0 X X X X X  
SG10 S36 - S39 1 0 0 1 X X X X X  
SG11 S40 - S43 1 0 1 0 X X X X X  
SG12 S44 - S47 1 0 1 1 X X X X X  
SG13 S48 - S51 1 1 0 0 X X X X X  
SG14 S52 - S55 1 1 0 1 X X X X X  
SG15 S56 - S59 1 1 1 0 X X X X X  
1 1 1 1 0 0 X X X  
SG16 S60 - S62 1 1 1 1 0 1 X X X  
1 1 1 1 1 0 X X X  
SG17  
SG18  
SG19  
SG20  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
128  
SG6 S11 - S14 0 0 1 0 X X X X X  
SG7 S15 - S18 0 0 1 1 X X X X X  
SG8 S19 - S22 0 1 0 0 X X X X X  
SG9 S23 - S26 0 1 0 1 X X X X X  
SG10 S27 - S30 0 1 1 0 X X X X X  
SG11 S31 - S34 0 1 1 1 X X X X X  
SG12 S35 - S38 1 0 0 0 X X X X X  
SG13 S39 - S42 1 0 0 1 X X X X X  
SG14 S43 - S46 1 0 1 0 X X X X X  
SG15 S47 - S50 1 0 1 1 X X X X X  
SG16 S51 - S54 1 1 0 0 X X X X X  
SG17 S55 - S58 1 1 0 1 X X X X X  
SG18 S59 - S62 1 1 1 0 X X X X X  
1 1 1 1 0 0 X X X  
96  
S63  
S64  
S65  
S66  
1 1 1 1 1 1 0 X X  
1 1 1 1 1 1 1 0 0  
1 1 1 1 1 1 1 0 1  
1 1 1 1 1 1 1 1 X  
16  
4
4
SG19 S63 - S65 1 1 1 1 0 1 X X X  
1 1 1 1 1 0 X X X  
SG20  
96  
32  
8
S66  
1 1 1 1 1 1 X X X  
viously protected sector groups. This function can  
be implemented either in-system or by using pro-  
gramming equipment. Note that to unprotect any  
sector, all unprotected sector groups must first be  
protected prior to the first sector unprotect write  
cycle. Also, the unprotect procedure will cause  
all sectors to become unprotected, thus, sector  
groups that require protection must be protected  
again after the unprotect procedure is run.  
tors can be programmed or erased by invoking  
the appropriate commands (see Device Com-  
mands section). Once VID is removed from RE-  
SET#, all the previously protected sector groups  
are protected again. Figure 5 illustrates the algo-  
rithm.  
NOTE: If WP#/ACC = VIL, the boot sectors remain pro-  
tected.  
Electronic ID Operation (High Voltage Method)  
This procedure requires VID on the RESET# pin  
and uses standard microprocessor bus cycle tim-  
ing to implement sector unprotection. The flow  
chart in Figure 4 illustrates the algorithm.  
The Electronic ID mode provides manufacturer  
and device identification, sector protection verifi-  
cation and Sec2 region protection status through  
identifier codes output on DQ[15:0]. This mode is  
intended primarily for programming equipment to  
automatically match a device to be programmed  
with its corresponding programming algorithm.  
Temporary Sector Unprotect Operation  
This feature allows temporary unprotection of pre-  
viously protected sector groups to allow changing  
the data in-system. Temporary Sector Unprotect  
mode is activated by setting the RESET# pin to  
VID. While in this mode, formerly protected sec-  
Two methods are provided for accessing the Elec-  
tronic ID data. The first requires VID on address  
pin A[9], with additional requirements for obtain-  
r1.3/May 02  
13  
HY29LV320  
START  
Wait 150 us  
RESET# = VIH  
RESET# = VID  
WP#/ACC VIH  
=
Verify Sector Group Protect:  
Write 0x40 to Address  
Write Reset Command  
Wait 1 us  
Read from Address  
SECTOR GROUP  
PROTECT COMPLETE  
First Write Cycle:  
Write 0x60 to device  
NO  
YES  
Data = 0x01?  
TRYCNT = 25?  
TRYCNT = 1  
NO  
YES  
Increment TRYCNT  
Set Address:  
A[20:12] = Address of Sector  
Group to be Protected  
A[6] = 0, A[1] = 1, A[0] = 0  
DEVICE FAILURE  
NO  
Protect Another  
Sector Group?  
Sector Group Protect:  
Write 0x60 to Address  
YES  
Figure 3. Sector Group Protect Algorithm  
START  
Set Address:  
A[20:12] = Address of  
Sector Group SNUM  
A[6] = 1, A[1] = 1, A[0] = 0  
Note: All sector groups  
must be protected prior to  
sector unprotection  
RESET# = VIH  
TRYCNT = 1  
SNUM = 0  
Write Reset Command  
Verify Unprotect:  
Write 0x40 to Address  
SECTOR UNPROTECT  
COMPLETE  
RESET# = VID  
Read from Address  
WP#/ACC  
= VIH  
Wait 1 us  
NO  
YES  
Data = 0x00?  
TRYCNT = 1000?  
First Write Cycle:  
Write 0x60 to device  
NO  
YES  
Set Address:  
Increment TRYCNT  
A[6] = 1, A[1] = 1, A[0] = 0  
YES  
DEVICE FAILURE  
SNUM = 20?  
Sector Unprotect:  
Write 0x60 to Address  
NO  
Wait 15 ms  
SNUM = SNUM + 1  
Figure 4. Sector Unprotect Algorithm  
r1.3/May 02  
14  
HY29LV320  
ing specific data items listed in Table 5. The Elec-  
tronic ID data can also be obtained by the host  
through specific commands issued via the com-  
mand register, as described later in the Device  
Commandssection of this data sheet.  
START  
RESET# = VID  
(All protected sectors  
become unprotected)  
While in the high-voltage Electronic ID mode, the  
system may read at specific addresses to obtain  
certain device identification and status informa-  
tion:  
Perform Program or Erase  
Operations  
n A read cycle at address 0xXXX00 retrieves the  
RESET# = VIH  
(All previously protected  
sectors return to protected  
state)  
manufacturer code.  
n A read cycle at address 0xXXX01 returns the  
device code.  
TEMPORARY SECTOR  
n A read cycle containing a sector address (SA)  
in A[20:12] and the address 0x04 in A[7:0] re-  
turns 0x01 if that sector is protected, or 0x00 if  
it is unprotected.  
UNPROTECT COMPLETE  
Figure 5. Temporary Sector Unprotect  
Algorithm  
n A read cycle at address 0xXXX03 returns 0x80  
if the Sec2 region is protected and locked at  
the factory and 0x00 if it is not.  
DEVICE COMMANDS  
Table 8. Composition of Command Sequences  
Device operations are initiated by writing desig-  
nated address and data command sequences into  
the device. Commands are routed to the com-  
mand register for execution. This register is auto-  
matically selected as the destination for all write  
operations and does not need to be explicitly ad-  
dressed. Addresses are latched on the falling  
edge of WE# or CE#, whichever happens later.  
Data is latched on the rising edge of WE# or CE#,  
whichever happens first.  
Number of Bus Cycles  
Command  
Sequence  
Unlock Command  
Data  
Read  
Reset  
Enter Sec2 Region  
Exit Sec2 Region  
Program  
0
0
2
2
2
2
0
1
1
1
1
1
Note 1  
0
0
1
1
0
Unlock Bypass  
Unlock Bypass  
Reset  
Unlock Bypass  
Program  
Chip Erase  
Sector Erase  
Erase Suspend  
Erase Resume  
Electronic ID  
CFI Query  
A command sequence is composed of one, two  
or three of the following sub-segments: an unlock  
cycle, a command cycle and a data cycle. Table  
8 summarizes the composition of the valid com-  
mand sequences implemented in the HY29LV320,  
and these sequences are fully described in Table  
9 and in the sections that follow.  
0
0
1
1
1
1
4
4
0
0
2
0
1
1
1
1
1
1
1
1 (Note 2)  
0
0
Writing incorrect address and data values or writ-  
ing them in the improper sequence resets the de-  
vice to the Read mode.  
Note 3  
Note 4  
Notes:  
1. Any number of Flash array read cycles are permitted.  
2. Additional data cycles may follow. See text.  
Reading Data  
3. Any number of Electronic ID read cycles are permitted.  
4. Any number of CFI data read cycles are permitted.  
The device automatically enters the read array  
mode after device power-up, after the RESET#  
input is asserted and upon the completion of cer-  
tain commands. Commands are not required to  
r1.3/May 02  
15  
HY29LV320  
tion). This aborts the command and resets the  
device to the Read mode. Once erasure be-  
gins, however, the device ignores the Reset  
command until the operation is complete.  
retrieve data in this mode. See Read Operation  
section for additional information.  
After the device accepts an Erase Suspend com-  
mand, the HY29LV320 enters the erase-suspend-  
read mode, after which the system can read data  
from any non-erase-suspended sector. After com-  
pleting a programming operation in the Erase  
Suspend mode, the system may once again read  
array data with the same exception. See the Erase  
Suspend/Erase Resume Commands section for  
more information.  
n In a Program command sequence, the Reset  
command may be written between the se-  
quence cycles before programming actually be-  
gins. This aborts the command and resets the  
device to the Read mode, or to the Erase Sus-  
pend mode if the Program command sequence  
is written while the device is in the Erase Sus-  
pend mode. Once programming begins, how-  
ever, the device ignores the Reset command  
until the operation is complete.  
Reset Command  
Writing the Reset command resets the sectors to  
the Read or Erase-Suspend mode. Address bits  
are dont cares for this command.  
n The Reset command may be written between  
the cycles in an Electronic ID command se-  
quence to abort that command. As described  
above, once in the Electronic ID mode, the  
Reset command must be written to return to  
the array Read mode.  
As described above, a Reset command is not nor-  
mally required to begin reading array data. How-  
ever, a Reset command must be issued in order  
to read array data in the following cases:  
Note: The Reset command does not return the device  
from Sec2 Region access to normal array access. See  
descriptions of Enter/Exit Sec2 Region commands for  
additional information.  
n If the device is in the Electronic ID mode, a  
Reset command must be written to return to  
the Read array mode. If the device was in the  
Erase Suspend mode when the device entered  
the Electronic ID mode, writing the Reset com-  
mand returns the device to the Erase Suspend  
mode.  
Enter/Exit Sec2 Region Command Sequences  
The system can access the Sec2 region of the  
device by issuing the Enter Sec2 Region Command  
sequence. The device continues to access the  
Sec2 region until the system issues the Exit Sec2  
Region Command sequence, which returns the  
device to normal operation.  
Note: When in the Electronic ID bus operation mode,  
the device returns to the Read array mode when VID is  
removed from the A[9] pin. The Reset command is not  
required in this case.  
n If the device is in the CFI Query mode, a Reset  
command must be written to return to the ar-  
ray Read mode.  
Note that a hardware reset will reset the device to  
the Read Array mode.  
Program Command Sequence  
n If DQ[5] (Exceeded Time Limit) goes High dur-  
ing a program or erase operation, a Reset com-  
mand must be invoked to return the sectors to  
the Read mode (or to the Erase Suspend mode  
if the device was in Erase Suspend when the  
Program command was issued).  
The system programs the device a word at a time  
by issuing the appropriate four-cycle Program  
Command sequence as shown in Table 9. The  
sequence begins by writing two unlock cycles, fol-  
lowed by the program setup command and, lastly,  
the program address and data. This initiates the  
Automatic Program algorithm that automatically  
provides internally generated program pulses and  
verifies the programmed cell margin. The host is  
not required to provide further controls or timings  
during this operation. When the Automatic Pro-  
gram algorithm is complete, the device returns to  
the reading array data mode. Several methods  
are provided to allow the host to determine the  
The Reset command may also be used to abort  
certain command sequences:  
n In a Sector Erase or Chip Erase command se-  
quence, the Reset command may be written  
at any time before erasing actually begins, in-  
cluding, for the Sector Erase command, be-  
tween the cycles that specify the sectors to be  
erased (see Sector Erase command descrip-  
r1.3/May 02  
16  
Table 9. HY29LV320 Command Sequences  
Bus Cycles 1, 2, 3, 4  
Third Fourth  
First  
Second  
Fifth  
Sixth  
Write  
Command Sequence  
Cycles  
Add  
Data  
Add  
Data  
Add  
Data  
Add  
Data Add  
Data  
Add  
Data  
Read  
0
RA  
RD  
Reset7  
1
3
4
4
3
2
2
6
6
1
1
3
3
XXX  
555  
555  
555  
555  
XXX  
XXX  
555  
555  
XXX  
XXX  
555  
555  
F0  
AA  
AA  
AA  
AA  
90  
Enter Sec 2 Region  
Exit Sec 2 Region  
Normal Program  
Unlock Bypass  
Unlock Bypass Reset6  
Unlock Bypass Program  
Chip Erase  
2AA  
2AA  
2AA  
2AA  
XXX  
PA  
55  
55  
55  
55  
00  
PD  
55  
55  
555  
555  
555  
555  
88  
90  
A0  
20  
00  
XXX  
PA  
PD  
5
A0  
AA  
AA  
B0  
30  
2AA  
2AA  
555  
555  
80  
80  
555  
555  
AA  
AA  
2AA  
2AA  
55  
55  
555  
SA  
10  
30  
Sector Erase 9  
Erase Suspend 7  
Erase Resume 8  
Manufacturer Code  
Device Code  
AA  
AA  
2AA  
2AA  
55  
55  
555  
555  
90  
90  
XXX00 00AD  
XXX01 Bottom Boot = 227D, Top Boot = 227E  
XX00 = Unprotected Sector  
(SA)X02  
Sector Protect Verify  
3
555  
AA  
2AA  
2AA  
55  
555  
555  
90  
XX01 = Protected Sector  
XX00 = NOT protected and locked at factory  
XXX03  
Sec2 Region Indicator Bit  
55  
90  
3
555  
AA  
98  
XX80 = Protected and locked at factory  
Common Flash Interface (CFI) Query 10  
XXX55  
1
Legend:  
X = Dont Care  
RA/RD = Memory address/data for the read operation  
PA/PD = Memory address/data for the program operation  
SA = A[20:12], sector address of the sector to be erased or verified (see Tables 1 and 2).  
Notes:  
1. All values are in hexadecimal.  
2. All bus cycles are write operations except all cycles of the Read command and the fourth cycle of Electronic ID command.  
3. Data bits DQ[15:8] are dont cares except for PDin program cycles.  
4. Address is A[10:0]. Other (upper) address bits are dont cares except when SAor PAis required.  
5. The Unlock Bypass command is required prior to the Unlock Bypass Program command.  
6. The Unlock Bypass Reset command is valid only while the device is in the Unlock Bypass mode.  
7. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the Electronic  
ID mode, while in the Erase Suspend mode.  
8. The Erase Resume command is valid only during the Erase Suspend mode.  
9. Multiple sectors may be specified for erasure. See command description.  
10.See CFI section of specification for additional information.  
11.See Electronic ID section of specification for additional information.  
HY29LV320  
status of the programming operation, as described  
in the Write Operation Status section.  
unlock write cycles followed by a third write cycle  
containing the unlock bypass command, 0x20.  
The device then enters Unlock Bypass mode. In  
this mode, a two-cycle Unlock Bypass Program  
Command sequence is used instead of the stan-  
dard four-cycle sequence to invoke a program-  
ming operation. The first cycle in this sequence  
contains the unlock bypass program command,  
0xA0, and the second cycle specifies the program  
address and data, thus eliminating the initial two  
unlock cycles required in the standard Program  
Command sequence. Additional data is pro-  
grammed in the same manner. The unlock by-  
pass mode does not affect normal read operations.  
Commands written to the device during execution  
of the Automatic Program algorithm are ignored.  
Note that a hardware reset immediately terminates  
the programming operation (see Reset Operation  
Timings). To ensure data integrity, the user should  
reinitiate the aborted Program Command se-  
quence after the reset operation is complete.  
Programming is allowed in any sequence. Only  
erase operations can convert a stored 0to a 1.  
Thus, a bit cannot be programmed from a 0back  
to a 1. Attempting to do so will cause the  
HY29LV320 to halt the operation and set DQ[5] to  
1, or cause the Data# Polling algorithm to indi-  
cate the operation was successful. However, a  
succeeding read will show that the data is still 0.  
During the unlock bypass mode, only the Unlock  
Bypass Program and the Unlock Bypass Reset  
commands are valid. To exit the Unlock Bypass  
mode, the host must issue the two-cycle Unlock  
Bypass Reset command sequence shown in Table  
9.  
Figure 6 illustrates the programming operation.  
Unlock Bypass Command Sequence  
Figure 6 illustrates the procedures for the normal  
and unlock bypass program operations.  
Unlock bypass provides a faster method than the  
normal Program Command for the host system to  
program the array. As shown in Table 9, the Un-  
lock Bypass Command sequence consists of two  
The device automatically enters the unlock bypass  
mode when it is placed in Accelerate mode via  
the ACC pin.  
START  
Check Programming Status  
(See Write Operation Status  
Section)  
DQ[5] Error Exit  
NO  
Enable Fast  
Programming?  
Programming Verified  
YES  
NO  
Last Word/Byte  
Done?  
Issue UNLOCK BYPASS  
Command  
YES  
Setup Next Address/Data for  
Program Operation  
NO  
Unlock Bypass  
Mode?  
YES  
NO  
Unlock Bypass  
Mode?  
Issue UNLOCK BYPASS  
RESET Command  
Issue NORMAL PROGRAM  
Command  
YES  
Issue UNLOCK BYPASS  
PROGRAM Command  
PROGRAMMING  
COMPLETE  
GO TO ERROR  
RECOVERY PROCEDURE  
Figure 6. Normal and Unlock Bypass Programming Procedures  
r1.3/May 02  
18  
HY29LV320  
Chip Erase Command Sequence  
Sector Erase Command Sequence  
The Chip Erase Command sequence consists of  
two unlock cycles, followed by a set-up command,  
two additional unlock cycles and then the Chip  
Erase Command. This sequence invokes the  
Automatic Chip Erase algorithm which automati-  
cally preprograms (if necessary) and verifies the  
entire memory for an all zero data pattern before  
electrical erase. The host system is not required  
to provide any controls or timings during these  
operations.  
The Sector Erase Command sequence consists  
of two unlock cycles, followed by a set-up com-  
mand, two additional unlock cycles and then the  
Sector Erase Command, which specifies which  
sector is to be erased. This sequence invokes  
the Automatic Sector Erase algorithm which auto-  
matically preprograms (if necessary) and verifies  
the specified sector for an all zero data pattern  
before electrical erase. The host system is not  
required to provide any controls or timings during  
these operations.  
If all sectors in the device are protected, the de-  
vice returns to reading array data after approxi-  
mately 100 μs. If at least one sector is unpro-  
tected, the erase operation erases the unprotected  
sectors, and ignores the command for the sectors  
that are protected. Reads from the device during  
operation of the Automatic Chip Erase Algorithm  
return status data. See Write Operation Status  
section of this specification.  
After the sector erase command cycle (sixth cycle)  
of the command sequence is issued, a sector  
erase time-out of 50 μs (min) begins, measured  
from the rising edge of the final WE# pulse in the  
command sequence. During this time, an addi-  
tional sector address and Sector Erase Command  
may be written into an internal sector erase buffer.  
This buffer may be loaded in any sequence, and  
the number of sectors designated for erasure may  
be from one sector to all sectors. The only re-  
striction is that the time between these additional  
cycles must be less than 50 μs, otherwise era-  
sure may begin before the last address and com-  
mand are accepted. To ensure that all commands  
are accepted, it is recommended that host pro-  
cessor interrupts be disabled during the time that  
the additional sector erase commands are being  
issued and then be re-enabled afterwards.  
Commands written to the device during execution  
of the Automatic Chip Erase algorithm are ignored.  
Note that a hardware reset immediately terminates  
the chip erase operation (see Hardware Reset Tim-  
ings). To ensure data integrity, the user should  
reinitiate the aborted Chip Erase Command se-  
quence after the reset operation is complete.  
When the Automatic Chip Erase algorithm is com-  
plete, the device returns to the reading array data  
mode. Several methods are provided to allow the  
host to determine the status of the erase opera-  
tion, as described in the Write Operation Status  
section.  
The system can monitor DQ[3] to determine if the  
50 μs sector erase time-out has expired, as de-  
scribed in the Write Operation Status section. If  
the time between additional sector erase com-  
mands can be assured to be less than the time-  
out, the system need not monitor the timeout.  
Figure 7 illustrates the chip erase procedure.  
Note: Any command other than Sector Erase or Erase  
Suspend during the time-out period resets the device to  
reading array data. The system must then rewrite the  
command sequence, including any additional sector  
addresses and commands. Once the sector erase op-  
eration itself has begun, only the Erase Suspend com-  
mand is valid. All other commands are ignored.  
START  
Issue CHIP ERASE  
Command Sequence  
Check Erase Status  
DQ[5] Error Exit  
(See Write Operation Status  
As for the chip erase command, note that a hard-  
ware reset immediately terminates the erase op-  
eration (see Hardware Reset Timings). To ensure  
data integrity, the aborted sector erase command  
sequence should be reissued once the reset op-  
eration is complete.  
Section)  
Normal Exit  
GO TO  
CHIP ERASE COMPLETE  
ERROR RECOVERY  
Figure 7. Chip Erase Procedure  
r1.3/May 02  
19  
HY29LV320  
command sequence, and is ignored if it is issued  
during chip erase or programming operations.  
If all sectors designated for erasing are protected,  
the device returns to reading array data after ap-  
proximately 100 μs. If at least one designated  
sector is unprotected, the erase operation erases  
the unprotected sectors, and ignores the command  
for the sectors that are protected. Read array  
operations cannot take place until the Automatic  
Erase algorithm terminates, or until the erase op-  
eration is suspended. Read operations while the  
algorithm is in progress provide status data. When  
the Automatic Erase algorithm is complete, the  
device returns the erased sector(s) to the Read  
(array data) mode.  
The HY29LV320 requires a maximum of 20 μs to  
suspend the erase operation if the erase suspend  
command is issued during active sector erasure.  
However, if the command is written during the  
sector erase time-out, the time-out is terminated  
and the erase operation is suspended immediately.  
Once the erase operation has been suspended,  
the system can read array data from or program  
data into any sector that is not designated for era-  
sure (protected sectors cannot be programmed).  
Normal read and write timings and command defi-  
nitions apply. Reading at any address within erase-  
suspended sectors produces status data on  
DQ[7:0]. The host can use DQ[7], or DQ[6] and  
DQ[2] together, to determine if a sector is actively  
erasing or is erase-suspended. See Write Op-  
eration Statusfor information on these status bits.  
Several methods are provided to allow the host to  
determine the status of the erase operation, as  
described in the Write Operation Status section.  
Figure 8 illustrates the sector erase procedure.  
Erase Suspend/Erase Resume Commands  
After an erase-suspended program operation is  
complete, the device returns to the erase-sus-  
pended read state and the host can initiate an-  
other programming operation (or read operation)  
within non-suspended sectors. The host can de-  
termine the status of a program operation during  
the erase-suspended state just as in the standard  
programming operation.  
The erase suspend command allows the system  
to interrupt a sector erase operation to program  
data into, or to read data from, any sector not  
designated for erasure. The command causes  
the erase operation to be suspended in all sec-  
tors designated for erasure. This command is valid  
only during the sector erase operation, including  
during the 50 μs time-out period at the end of the  
START  
Check Erase Status  
DQ[5] Error Exit  
(See Write Operation Status  
Section)  
Normal Exit  
Write First Five Cycles of  
SECTOR ERASE  
Command Sequence  
GO TO  
ERASE COMPLETE  
Setup First (or Next) Sector  
Address for Erase Operation  
ERROR RECOVERY  
Sectors that require erasure but  
which were not specified in this  
erase cycle must be erased later  
using a new command sequence  
Write Last Cycle (SA/0x30)  
of SECTOR ERASE  
Command Sequence  
N O  
Sector Erase  
Time-out (DQ[3])  
Expired?  
Erase An  
Additional Sector?  
YES  
YES  
N O  
Figure 8. Sector Erase Procedure  
r1.3/May 02  
20  
HY29LV320  
The host may also write the Electronic ID Com-  
mand sequence when the chip is in the Erase  
Suspend mode. The device allows reading Elec-  
tronic ID codes even at addresses within erasing  
sectors, since the codes are not stored in the  
memory array. When the device exits the Elec-  
tronic ID mode, the device reverts to the Erase  
Suspend mode, and is ready for another valid  
operation. See Electronic ID Mode section for  
more information.  
n A read cycle at address 0xXXX00 retrieves the  
manufacturer code.  
n A read cycle at address 0xXXX01 in returns  
the device code.  
n A read cycle containing a sector address (SA)  
in A[20:12] and the address 0x02 in A[7:0] re-  
turns 0x01 if that sector is protected, or 0x00 if  
it is unprotected.  
n A read cycle at address 0xXXX03 returns 0x80  
if the Sec2 region is protected and locked at  
the factory and returns 0x00 if it is not.  
The system must write the Erase Resume com-  
mand to exit the Erase Suspend mode and con-  
tinue the sector erase operation. Further writes of  
the Resume command are ignored. Another Erase  
Suspend command can be written after the de-  
vice has resumed erasing.  
The system must write the Reset command to exit  
the Electronic ID mode and return the bank to the  
normal Read mode, or to the Erase-Suspended  
read mode if the device was in that mode when  
the Electronic ID command was invoked. In the  
latter case, an Erase Resume command to that  
bank will continue the suspended erase operation.  
Note: If an erase operation is started while in the Sec2  
region and then suspended to do other operations, the  
host must return the device to the Sec2 region before  
issuing the Erase Resume command. Failure to do this  
may result in the wrong sector being erased.  
Query Command and Common Flash Inter-  
face (CFI) Mode  
Electronic ID Command  
The HY29LV320 is capable of operating in the  
Common Flash Interface (CFI) mode. This mode  
allows the host system to determine the manufac-  
turer of the device, its operating parameters, its  
configuration and any special command codes that  
the device may accept. With this knowledge, the  
system can optimize its use of the chip by using  
appropriate timeout values, optimal voltages and  
commands necessary to use the chip to its full  
advantage.  
The Electronic ID mode provides manufacturer  
and device identification and sector protection veri-  
fication through identifier codes output on  
DQ[15:0]. This mode is intended primarily for pro-  
gramming equipment to automatically match a  
device to be programmed with its corresponding  
programming algorithm.  
Two methods are provided for accessing the Elec-  
tronic ID data. The first requires VID on address  
pin A[9], as described previously in the Device  
Operations section.  
Two commands are employed in association with  
CFI mode. The first places the device in CFI mode  
(Query command) and the second takes it out of  
CFI mode (Reset command). These are described  
in Table 10.  
The Electronic ID data can also be obtained by the  
host through specific commands issued via the com-  
mand register, as shown in Table 9. This method  
does not require VID. The Electronic ID command  
sequence may be issued while the device is in the  
Read mode or in the Erase Suspend Read mode.  
The command may not be written while the device  
is actively programming or erasing.  
The single cycle Query command is valid only  
when the device is in the Read mode, including  
during Erase Suspend and Standby states and  
while in Electronic ID command mode, but is ig-  
nored otherwise. The command is not valid while  
the HY29LV320 is in the Electronic ID bus opera-  
tion mode. Read cycles at appropriate addresses  
while in the Query mode provide CFI data as de-  
scribed later in this section. Write cycles are ig-  
nored, except for the Reset command.  
The Electronic ID command sequence is initiated  
by writing two unlock cycles, followed by a third  
write cycle that contains the Electronic ID com-  
mand. The device then enters the Electronic ID  
mode, and the system may read at any address  
any number of times without initiating another com-  
mand sequence.  
The Reset command returns the device from the  
CFI mode to the array Read mode (even if it was  
r1.3/May 02  
21  
HY29LV320  
in the Electronic ID mode when the Query com-  
mand was issued), or to the Erase Suspend mode  
if the device was in that mode prior to entering  
CFI mode. The Reset command is valid only when  
the device is in the CFI mode and as otherwise  
described for the normal Reset command.  
Tables 10 - 13 specify the data provided by the  
HY29LV320 during CFI mode. Data at unspeci-  
fied addresses reads out as 0x00. Note that a  
value of 0x00 for a data item normally indicates  
that the function is not supported. All values in  
these tables are in hexadecimal notation.  
Table 10. CFI Mode: Identification Data Values  
Description  
Address  
Data  
10  
11  
12  
0051  
0052  
0059  
Query-unique ASCII string "QRY"  
13  
14  
0002  
0000  
Primary vendor command set and control interface ID code  
Address for primary algorithm extended query table  
15  
16  
0040  
0000  
17  
18  
0000  
0000  
Alternate vendor command set and control interface ID code (none)  
Address for secondary algorithm extended query table (none)  
19  
1A  
0000  
0000  
r1.3/May 02  
22  
HY29LV320  
Table 11. CFI Mode: System Interface Data Values  
Description  
Address  
1B  
Data  
0027  
0036  
0000  
0000  
0004  
0000  
0009  
000F  
0005  
0000  
0004  
0000  
VCC supply, minimum (2.7V)  
VCC supply, maximum (3.6V)  
1C  
1D  
1E  
VPP supply, minimum (none)  
VPP supply, maximum (none)  
Typical timeout for single word/byte write (2N μs)  
Typical timeout for maximum size buffer write (2N μs)  
Typical timeout for individual block erase (2N ms)  
Typical timeout for full chip erase (2N ms)  
Maximum timeout for single word/byte write (2N x Typ)  
Maximum timeout for maximum size buffer write (2N x Typ)  
Maximum timeout for individual block erase (2N x Typ)  
Maximum timeout for full chip erase (not supported)  
1F  
20  
21  
22  
23  
24  
25  
26  
Table 12. CFI Mode: Device Geometry Data Values  
Description  
Address  
Data  
Device size (2N bytes)  
27  
0016  
28  
29  
0001  
0000  
Flash device interface code (01 = asynchronous x16)  
2A  
2B  
0000  
0000  
Maximum number of bytes in multi-byte write (not supported)  
Number of erase block regions  
2C  
0004  
2D  
2E  
2F  
30  
0000  
0000  
0040  
0000  
Erase block region 1 information  
[2E, 2D] = # of blocks in region - 1  
[30, 2F] = size in multiples of 256-bytes  
31  
32  
33  
34  
0001  
0000  
0020  
0000  
Erase block region 2 information  
Erase block region 3 information  
Erase block region 4 information  
35  
36  
37  
38  
0000  
0000  
0080  
0000  
39  
3A  
3B  
3C  
003E  
0000  
0000  
0001  
r1.3/May 02  
23  
HY29LV320  
Table 13. CFI Mode: Vendor-Specific Extended Query Data Values  
Description  
Address  
Data  
40  
41  
42  
0050  
0052  
0049  
Query-unique ASCII string "PRI"  
Major version number, ASCII  
43  
44  
45  
46  
47  
48  
49  
0031  
0030  
0000  
0002  
0001  
0001  
0004  
Minor version number, ASCII  
Address sensitive unlock (0 = required, 1 = not required)  
Erase suspend(2 = to read and write)  
Sector protect (N = # of sectors/group)  
Temporary sector unprotect (1 = supported)  
Sector protect/unprotect scheme (4 = Am29LV800A method)  
Simultaneous R/W operation  
(xx = number of sectors in Bank 2: 0 = not supported)  
4A  
0000  
Burst mode type (0 = not supported)  
Page mode type (0 = not supported)  
ACC Supply minimum (11.5V)  
4B  
4C  
4D  
4E  
0000  
0000  
00B5  
00C5  
ACC Supply maximum (12.5V)  
0002 (BB)  
0003 (TB)  
Top/bottom boot version (BB = Bottom Boot, TB = Top Boot)  
4F  
WRITE OPERATION STATUS  
rithm is in progress or completed, or whether the  
device is in Erase Suspend mode. Data# Polling  
is valid after the rising edge of the final WE# pulse  
in the Program or Erase command sequence.  
The HY29LV320 provides a number of facilities to  
determine the status of a program or erase op-  
eration. These are the RY/BY# (Ready/Busy#)  
pin and certain bits of a status word which can be  
read from the device during the programming and  
erase operations. Table 11 summarizes the sta-  
tus indications and further detail is provided in the  
subsections which follow.  
The system must do a read at the program ad-  
dress to obtain valid programming status informa-  
tion on this bit. While a programming operation is  
in progress, the device outputs the complement  
of the value programmed to DQ[7]. When the pro-  
gramming operation is complete, the device out-  
puts the value programmed to DQ[7]. If a pro-  
gram operation is attempted within a protected  
sector, Data# Polling on DQ[7] is active for ap-  
proximately 1 μs, then the device returns to read-  
ing array data.  
RY/BY# - Ready/Busy#  
RY/BY# is an open-drain output pin that indicates  
whether a programming or erase Automatic Algo-  
rithm is in progress or has completed. A pull-up  
resistor to VCC is required for proper operation. RY/  
BY# is valid after the rising edge of the final WE#  
pulse in the corresponding command sequence.  
The host must read at an address within any non-  
protected sector specified for erasure to obtain  
valid erase status information on DQ[7]. During  
an erase operation, Data# Polling produces a 0”  
on DQ[7]. When the erase operation is complete,  
or if the device enters the Erase Suspend mode,  
Data# Polling produces a 1on DQ[7]. If all sec-  
tors selected for erasing are protected, Data#  
Polling on DQ[7] is active for approximately 100  
μs, then the device returns to reading array data.  
If at least one selected sector is not protected, the  
erase operation erases the unprotected sectors,  
If the output is Low (busy), the device is actively  
erasing or programming, including programming  
while in the Erase Suspend mode. If the output is  
High (ready), the device has completed the opera-  
tion and is ready to read array data in the normal or  
Erase Suspend modes, or it is in the Standby mode.  
DQ[7] - Data# Polling  
The Data# (Data Bar) Polling bit, DQ[7], indicates  
to the host system whether an Automatic Algo-  
r1.3/May 02  
24  
HY29LV320  
Table 14. Write and Erase Operation Status Summary 1  
Mode  
Operation  
Programming in progress  
Programming completed  
Erase in progress  
DQ[7]  
DQ[7]#  
Data  
0
DQ[6]  
Toggle  
Data 4  
Toggle  
Data 4  
DQ[5]  
0/1 2  
DQ[3]  
N/A  
DQ[2]  
RY/BY#  
N/A  
Data  
0
1
0
1
Data  
0/1 2  
Data  
1 3  
Normal  
Toggle  
Data 4  
Erase completed 5  
Data  
Data  
Data  
Read within erase suspended  
sector  
1
No toggle  
Data  
0
N/A  
Toggle  
Data  
1
1
Read within non-erase  
suspended sector  
Erase  
Data  
Data  
Data  
Suspend  
Programming in progress 6  
Programming completed 6  
DQ[7]#  
Data  
Toggle  
Data 4  
0/1 2  
N/A  
N/A  
0
1
Data  
Data  
Data  
Notes:  
1. A valid address is required when reading status information (except RY/BY#). For a programming operation, the ad-  
dress used for the read cycle should be the program address. For an erase operation, the address used for the read  
cycle should be any address within a non-protected sector marked for erasure (any address within a non-protected  
sector for the chip erase operation).  
2. DQ[5] status switches to a 1when a program or erase operation exceeds the maximum timing limit.  
3. A 1during sector erase indicates that the 50 μs time-out has expired and active erasure is in progress. DQ[3] is not  
applicable to the chip erase operation.  
4. Equivalent to No Togglebecause data is obtained in this state.  
5. Data (DQ[7:0]) = 0xFF immediately after erasure.  
6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).  
and ignores the command for the specified sec-  
tors that are protected.  
a protected sector, DQ[6] toggles for approximately  
1 μs after the program command sequence is writ-  
ten, then returns to reading array data.  
When the system detects that DQ[7] has changed  
from the complement to true data (or 0to 1for  
erase), it should do an additional read cycle to read  
valid data from DQ[7:0]. This is because DQ[7]  
may change asynchronously with respect to the  
other data bits while Output Enable (OE#) is as-  
serted low.  
While the Automatic Erase algorithm is operating,  
successive read cycles at any address cause  
DQ[6] to toggle. DQ[6] stops toggling when the  
erase operation is complete or when the device is  
placed in the Erase Suspend mode. The host may  
use DQ[2] to determine which sectors are erasing  
or erase-suspended (see below). After an Erase  
command sequence is written, if all sectors se-  
lected for erasing are protected, DQ[6] toggles for  
approximately 100 μs, then returns to reading ar-  
ray data. If at least one selected sector is not  
protected, the Automatic Erase algorithm erases  
the unprotected sectors, and ignores the selected  
sectors that are protected.  
Figure 9 illustrates the Data# Polling test algorithm.  
DQ[6] - Toggle Bit I  
Toggle Bit I on DQ[6] indicates whether an Auto-  
matic Program or Erase algorithm is in progress  
or complete, or whether the device has entered  
the Erase Suspend mode. Toggle Bit I may be read  
at any address, and is valid after the rising edge  
of the final WE# pulse in the Program or Erase  
command sequence, including during the sector  
erase time-out. The system may use either OE#  
or CE# to control the read cycles.  
DQ[2] - Toggle Bit II  
Toggle Bit II, DQ[2], when used with DQ[6], indi-  
cates whether a particular sector is actively eras-  
ing or whether that sector is erase-suspended.  
Toggle Bit II is valid after the rising edge of the  
final WE# pulse in the command sequence. The  
device toggles DQ[2] with each OE# or CE# read  
cycle.  
Successive read cycles at any address during an  
Automatic Program algorithm operation (including  
programming while in Erase Suspend mode) cause  
DQ[6] to toggle. DQ[6] stops toggling when the op-  
eration is complete. If a program address falls within  
r1.3/May 02  
25  
HY29LV320  
limit. This is a failure condition that indicates that  
the program or erase cycle was not successfully  
completed. DQ[5] status is valid only while DQ[7]  
or DQ[6] indicate that the Automatic Algorithm is  
in progress.  
START  
Read DQ[7:0]  
at Valid Address (Note 1)  
Test for DQ[7] = 1?  
for Erase Operation  
The DQ[5] failure condition will also be signaled if  
the host tries to program a 1to a location that is  
previously programmed to 0, since only an erase  
operation can change a 0to a 1.  
DQ[7] = Data?  
NO  
YES  
For both of these conditions, the host must issue  
a Reset command to return the device to the Read  
mode.  
NO  
DQ[5] = 1?  
YES  
Note: While DQ[5] indicates an error condition, no com-  
mands (except Reads) will be accepted by the device. If  
the device receives a command while DQ[5] is high, the  
first write cycle of that command will reset the error con-  
dition and the remaining write cycles of that command  
sequence will be ignored  
Read DQ[7:0]  
at Valid Address (Note 1)  
Test for DQ[7] = 1?  
for Erase Operation  
DQ[7] = Data?  
(Note 2)  
DQ[3] - Sector Erase Timer  
YES  
After writing a Sector Erase command sequence,  
the host may read DQ[3] to determine whether or  
not an erase operation has begun. When the  
sector erase time-out expires and the sector erase  
operation commences, DQ[3] switches from a 0’  
to a 1. Refer to the Sector Erase Command”  
section for additional information. Note that the  
sector erase timer does not apply to the Chip Erase  
command.  
NO  
PROGRAM/ERASE  
EXCEEDED TIME ERROR  
PROGRAM/ERASE  
COMPLETE  
Notes:  
1. During programming , the program address. During sector erase , an  
address within any non-protected sector specified for erasure. During  
chip erase , an address within any non-protected sector.  
2. Recheck DQ[7] since it may change asynchronously to DQ[5].  
Figure 9. Data# Polling Test Algorithm  
DQ[2] toggles when the host reads at addresses  
within sectors that have been specified for era-  
sure, but cannot distinguish whether the sector is  
actively erasing or is erase-suspended. DQ[6],  
by comparison, indicates whether the device is ac-  
tively erasing or is in Erase Suspend, but cannot  
distinguish which sectors are specified for erasure.  
Thus, both status bits are required for sector and  
mode information.  
After the initial Sector Erase command sequence  
is issued, the system should read the status on  
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to  
ensure that the device has accepted the command  
sequence, and then read DQ[3]. If DQ[3] is a 1,  
the internally controlled erase cycle has begun and  
all further sector erase data cycles or commands  
(other than Erase Suspend) are ignored until the  
erase operation is complete. If DQ[3] is a 0, the  
device will accept a sector erase data cycle to mark  
an additional sector for erasure. To ensure that  
the data cycles have been accepted, the system  
software should check the status of DQ[3] prior to  
and following each subsequent sector erase data  
cycle. If DQ[3] is high on the second status check,  
the last data cycle might not have been accepted.  
Figure 10 illustrates the operation of Toggle Bits I  
and II.  
DQ[5] - Exceeded Timing Limits  
DQ[5] is set to a 1when the program or erase  
time has exceeded a specified internal pulse count  
r1.3/May 02  
26  
HY29LV320  
START  
DQ[5] = 1?  
YES  
Read DQ[7:0]  
at Valid Address (Note 1)  
NO  
Read DQ[7:0]  
Read DQ[7:0]  
Read DQ[7:0]  
at Valid Address (Note 1)  
Read DQ[7:0]  
at Valid Address (Note 1)  
YES  
NO  
DQ[6] Toggled?  
(Note 2)  
NO  
DQ[6] Toggled?  
DQ[2] Toggled?  
YES  
NO  
(Note 4)  
NO  
(Note 3)  
YES  
PROGRAM/ERASE  
COMPLETE  
PROGRAM/ERASE  
EXCEEDED TIME ERROR  
SECTOR BEING READ  
IS IN ERASE SUSPEND  
SECTOR BEING READ  
IS NOT IN ERASE SUSPEND  
Notes  
:
1. During programming, the program address.  
During sector erase, an address within any sector scheduled for erasure.  
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.  
3. Use this path if testing for Program/Erase status.  
4. Use this path to test whether sector is in Erase Suspend mode.  
Figure 10. Toggle Bit I and II Test Algorithm  
HARDWARE DATA PROTECTION  
Write Pulse “Glitch” Protection  
The HY29LV320 provides several methods of pro-  
tection to prevent accidental erasure or program-  
ming which might otherwise be caused by spuri-  
ous system level signals during VCC power-up and  
power-down transitions, or from system noise.  
These methods are described in the sections that  
follow.  
Noise pulses of less than 5 ns (typical) on OE#,  
CE# or WE# do not initiate a write cycle.  
Logical Inhibit  
Write cycles are inhibited by asserting any one of  
the following conditions: OE# = VIL , CE# = VIH, or  
WE# = VIH. To initiate a write cycle, CE# and WE#  
must be a logical zero while OE# is a logical one.  
Command Sequences  
Commands that may alter array data require a  
sequence of cycles as described in Table 9. This  
provides data protection against inadvertent writes.  
Power-Up Write Inhibit  
If WE# = CE# = VIL and OE# = VIH during power up,  
the device does not accept commands on the rising  
edge of WE#. The internal state machine is auto-  
matically reset to the Read mode on power-up.  
Low VCC Write Inhibit  
To protect data during VCC power-up and power-  
down, the device does not accept write cycles  
when VCC is less than VLKO (typically 2.4 volts). The  
command register and all internal program/erase  
circuits are disabled, and the device resets to the  
Read mode. Writes are ignored until VCC is greater  
than VLKO. The system must provide the proper  
signals to the control pins to prevent unintentional  
Sector Protection  
Additional data protection is provided by the  
HY29LV320s sector protect feature, described  
previously, which can be used to protect sensitive  
areas of the Flash array from accidental or unau-  
thorized attempts to alter the data.  
writes when VCC is greater than VLKO  
.
r1.3/May 02  
27  
HY29LV320  
ABSOLUTE MAXIMUM RATINGS4  
Symbol  
Parameter  
Value  
Unit  
oC  
TSTG  
TBIAS  
Storage Temperature  
Ambient Temperature with Power Applied  
-65 to +150  
-65 to +125  
oC  
Voltage on Pin with Respect to VSS  
:
1
VCC  
-0.5 to +4.0  
-0.5 to +12.5  
-0.5 to (VCC + 0.5)  
V
V
V
VIN2  
A[9], OE#, WP#/ACC, RESET# 2  
All Other Pins 1  
IOS  
Output Short Circuit Current3  
200  
mA  
Notes:  
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to  
-2.0V for periods of up to 20 ns. See Figure 11. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage  
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 12.  
2. Minimum DC input voltage on pins A[9], WP#/ACC, OE#, and RESET# is -0.5 V. During voltage transitions, A[9], WP#/  
ACC, OE#, and RESET# may undershoot VSS to 2.0 V for periods of up to 20 ns. See Figure 11. Maximum DC input  
voltage on pins A[9], WP#/ACC, OE# and RESET# is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.  
3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.  
4. Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a  
stress rating only; functional operation of the device at these or any other conditions above those indicated in the  
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for  
extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS1  
Symbol  
TA  
Parameter  
Ambient Operating Temperature:  
Value  
Unit  
Commercial Temperature Devices  
Industrial Temperature Devices  
0 to +70  
-40 to +85  
oC  
oC  
VCC  
Operating Supply Voltage  
Note 2  
V
Notes:  
1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.  
2. See Valid Combinations table, page 43.  
20 ns  
20 ns  
20 ns  
VCC + 2.0 V  
0.8 V  
- 0.5 V  
VCC + 0.5 V  
2.0 V  
- 2.0 V  
20 ns  
20 ns  
20 ns  
Figure 11. Maximum Undershoot Waveform  
Figure 12. Maximum Overshoot Waveform  
r1.3/May 02  
28  
HY29LV320  
DC CHARACTERISTICS  
Parameter  
Description  
Test Setup 2  
VIN = VSS to VCC  
Min  
Typ  
Max  
±1.0  
35  
Unit  
μA  
ILI  
ILIT  
ILO  
Input Load Current  
A[9], Input Load Current  
Output Leakage Current  
A[9] = 12.5V  
μA  
VOUT = VSS to VCC  
±1.0  
16  
μA  
5 MHz  
1 MHz  
9
2
mA  
mA  
mA  
CE# = VIL,  
OE# = VIH,  
ICC1  
ICC2  
VCC Active Read Current1  
VCC Active Write Current3, 4  
4
CE# = VIL,OE# = VIH  
20  
30  
CE# = VCC ± 0.3 V,  
RESET# = VCC ± 0.3 V,  
WP#/ACC = VCC ± 0.3 V  
or VSS ± 0.3 V  
VCC CE# Controlled Deep  
Standby Current  
ICC3  
0.5  
5
μA  
RESET# = VSS ± 0.3 V,  
WP#/ACC = VCC ± 0.3 V  
or VSS ± 0.3 V  
VCC RESET# Controlled  
Deep Standby Current  
ICC4  
0.5  
0.5  
5
5
μA  
μA  
Automatic Sleep Mode  
Current5,  
VIH = VCC ± 0.3 V,  
VIL = VSS ± 0.3 V  
ICC5  
IACC  
VHH  
VCC  
5
10  
30  
mA  
mA  
V
Accelerated Program  
Current4  
CE# = VIL  
OE# = VIH  
15  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
-0.5  
0.8  
0.7 x VCC  
VCC + 0.3  
V
Voltage for Electronic ID and  
Temporary Sector Unprotect  
VID  
VHH  
VOL  
VCC = 3.0V ± 10%  
VCC = 3.0V ± 10%  
11.5  
11.5  
12.5  
12.5  
0.45  
V
V
V
V
Voltage for Program  
Acceleration  
VCC = VCC Min,  
IOL = 4.0 mA  
Output Low Voltage  
VCC = VCC Min,  
IOH = -2.0 mA  
VOH1  
VOH2  
0.85 x VCC  
Output High Voltage  
VCC = VCC Min,  
IOH = -100 μA  
VCC - 0.4  
2.3  
V
V
VLKO  
Low VCC Lockout Voltage4  
2.5  
Notes:  
1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. Typical VCC is 3.0 V.  
2. All maximum current specifications are tested with VCC = VCC Max unless otherwise noted.  
3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress.  
4. Not 100% tested.  
5. Automatic sleep mode is enabled when addresses remain stable for tACC + 50 ns (typical).  
r1.3/May 02  
29  
HY29LV320  
DC CHARACTERISTICS  
Zero Power Flash  
20  
15  
10  
5
0
0
500  
1000  
1500  
2000  
2500  
3000  
3500  
4000  
Time in ns  
Note: Addresses are switching at 1 MHz.  
Figure 13. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)  
3.6 V  
10  
8
2.7 V  
6
4
2
0
1
2
3
4
5
6
Frequency in MHz  
Note: TA = 25 °C.  
Figure 14. Typical ICC1 Current vs. Frequency  
r1.3/May 02  
30  
HY29LV320  
KEY TO SWITCHING WAVEFORMS  
WAVEFORM  
INPUTS  
OUTPUTS  
Steady  
Changing from H to L  
Changing from L to H  
Don't Care, Any Change Permitted  
Does Not Apply  
Changing, State Unknown  
Centerline is High Impedance State  
(High Z)  
TEST CONDITIONS  
Table 15. Test Specifications  
+ 3.3V  
- 80  
- 90 Unit  
- 12  
Test  
Condition  
- 70  
2.7  
KOhm  
Output Load  
1 TTL Gate  
100  
Output Load Capacitance (CL)  
Input Rise and Fall Times  
Input Signal Low Level  
30  
pF  
ns  
V
DEVICE  
UNDER  
TEST  
5
0.0  
3.0  
All diodes  
are  
1N3064  
or  
equivalent  
Input Signal High Level  
V
6.2  
KOhm  
Low