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產(chǎn)品型號(hào)HY29LV400TT-55的Datasheet PDF文件預(yù)覽

HY29LV400  
4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory  
KEY FEATURES  
n Single Power Supply Operation  
– Read, program and erase operations from  
2.7 to 3.6 volts  
– Ideal for battery-powered applications  
n High Performance  
n Minimum 100,000 Write Cycles per Sector  
n Compatible With JEDEC standards  
Pinout and software compatible with  
single-power supply Flash devices  
Superior inadvertent write protection  
n Data# Polling and Toggle Bits  
Provide software confirmation of  
completion of program and erase  
operations  
– 70 and 90 ns access time versions for full  
voltage range operation  
– 55 ns access time version for operation  
from 3.0 to 3.6 volts  
n Ultra-low Power Consumption (Typical  
Values)  
n Ready/Busy# Pin  
Provides hardware confirmation of  
completion of program and erase  
operations  
– Automatic sleep mode current: 0.2 μA  
– Standby mode current: 0.2 μA  
– Read current: 7 mA (at 5 Mhz)  
– Program/erase current: 15 mA  
n Flexible Sector Architecture:  
– One 16 KB, two 8 KB, one 32 KB and  
seven 64 KB sectors in byte mode  
– One 8 KW, two 4 KW, one 16 KW and  
seven 32 KW sectors in word mode  
Top or bottom boot block configurations  
available  
n Erase Suspend/Erase Resume  
Suspends an erase operation to allow  
reading data from, or programming data  
to, a sector that is not being erased  
Erase Resume can then be invoked to  
complete suspended erasure  
n Hardware Reset Pin (RESET#) Resets the  
Device to Reading Array Data  
n Space Efficient Packaging  
48-pin TSOP and 48-ball FBGA packages  
n Sector Protection  
– Allows locking of a sector or sectors to  
prevent program or erase operations  
within that sector  
– Sectors lockable in-system or via  
programming equipment  
Temporary Sector Unprotect allows  
changes in locked sectors (requires high  
voltage on RESET# pin)  
LOGIC DIAGRAM  
18  
8
7
n Fast Program and Erase Times  
– Sector erase time: 0.5 sec typical for each  
sector  
A[17:0]  
CE#  
DQ[7:0]  
– Chip erase time: 5 sec typical  
– Byte program time: 9 μs typical  
– Word program time: 11 μs typical  
n Unlock Bypass Program Command  
– Reduces programming time when issuing  
multiple program command sequences  
n Automatic Erase Algorithm Preprograms  
and Erases Any Combination of Sectors  
or the Entire Chip  
DQ[14:8]  
OE#  
DQ[15]/A[-1]  
RY/BY#  
W E #  
RESET#  
BYTE#  
n Automatic Program Algorithm Writes and  
Verifies Data at Specified Addresses  
Preliminary  
Revision 1.0, November 2001  
HY29LV400  
GENERAL DESCRIPTION  
The HY29LV400 is a 4 Mbit, 3 volt-only, CMOS  
Flash memory organized as 524,288 (512K) bytes  
or 262,144 (256K) words that is available in 48-  
pin TSOP and 48-ball FBGA packages. Word-  
wide data (x16) appears on DQ[15:0] and byte-  
wide (x8) data appears on DQ[7:0].  
programmed without affecting the data contents  
of other sectors. Device erasure is initiated by  
executing the Erase Command sequence. This  
initiates an internal algorithm that automatically  
preprograms the array (if it is not already pro-  
grammed) before executing the erase operation.  
As during programming cycles, the device auto-  
matically times the erase pulse widths and veri-  
fies proper cell margin. Hardware Sector Protec-  
tion optionally disables both program and erase  
operations in any combination of the sectors of  
the memory array, while Temporary Sector Unpro-  
tect allows in-system erasure and code changes  
in previously protected sectors. Erase Suspend  
enables the user to put erase on hold for any pe-  
riod of time to read data from, or program data to,  
any sector that is not selected for erasure. True  
background erase can thus be achieved. The de-  
vice is fully erased when shipped from the factory.  
The HY29LV400 can be programmed and erased  
in-system with a single 3 volt VCC supply. Inter-  
nally generated and regulated voltages are pro-  
vided for program and erase operations, so that  
the device does not require a higher voltage VPP  
power supply to perform those functions. The de-  
vice can also be programmed in standard EPROM  
programmers. Access times as low as 70 ns over  
the full operating voltage range of 2.7 - 3.6 volts  
are offered for timing compatibility with the zero  
wait state requirements of high speed micropro-  
cessors. A 55 ns version operating from 3.0 to  
3.6 volts is also available. To eliminate bus con-  
tention, the HY29LV400 has separate chip enable  
(CE#), write enable (WE#) and output enable  
(OE#) controls.  
Addresses and data needed for the programming  
and erase operations are internally latched during  
write cycles, and the host system can detect  
completion of a program or erase operation by  
observing the RY/BY# pin, or by reading the DQ[7]  
(Data# Polling) and DQ[6] (toggle) status bits.  
Hardware data protection measures include a low  
VCC detector that automatically inhibits write op-  
erations during power transitions.  
The device is compatible with the JEDEC single-  
power-supply Flash command set standard. Com-  
mands are written to the command register using  
standard microprocessor write timings. They are  
then routed to an internal state-machine that con-  
trols the erase and programming circuits. Device  
programming is performed a byte/word at a time  
by executing the four-cycle Program Command  
write sequence. This initiates an internal algorithm  
that automatically times the program pulse widths  
and verifies proper cell margin. Faster program-  
ming times can be achieved by placing the  
HY29LV400 in the Unlock Bypass mode, which  
requires only two write cycles to program data in-  
stead of four.  
After a program or erase cycle has been com-  
pleted, or after assertion of the RESET# pin (which  
terminates any operation in progress), the device  
is ready to read data or to accept another com-  
mand. Reading data out of the device is similar to  
reading from other Flash or EPROM devices.  
Two power-saving features are embodied in the  
HY29LV400. When addresses have been stable  
for a specified amount of time, the device enters  
the automatic sleep mode. The host can also place  
the device into the standby mode. Power con-  
sumption is greatly reduced in both these modes.  
The HY29LV400s sector erase architecture allows  
any number of array sectors to be erased and re-  
Rev. 1.0/Nov. 01  
2
HY29LV400  
BLOCK DIAGRAM  
DQ[15:0]  
A[17:0, 1]  
DQ[15:0]  
STATE  
CONTROL  
ERASE VOLTAGE  
GENERATOR AND  
SECTOR SWITCHES  
I/O BUFFERS  
DATA LATCH  
Y-GATING  
COMMAND  
REGISTER  
WE#  
CE#  
I/O CONTROL  
OE#  
PROGRAM  
VOLTAGE  
GENERATOR  
BYTE#  
RESET#  
RY/BY#  
Y-DECODER  
X-DECODER  
4 Mb FLASH  
MEMORY  
ARRAY  
A[17:0, -1]  
VC C DETECTOR  
TIMER  
(11 Sectors)  
SIGNAL DESCRIPTIONS  
Name  
Type  
Description  
Address, active High. These 18 inputs, combined with the DQ[15]/A[-1] input in  
Byte mode, select one location within the array for read or write operations.  
A[17:0]  
Inputs  
Data Bus, active High. These pins provide an 8- or 16-bit data path for read  
and write operations. In Byte mode, DQ[15]/A[-1] is used as the LSB of the 19-bit  
byte address input. DQ[14:8] are unused and remain tri-stated in Byte mode.  
DQ[15]/A[-1], Inputs/Outputs  
DQ[14:0]  
Tri-state  
Byte Mode, active Low. Low selects Byte mode, High selects Word mode.  
BYTE#  
Input  
Chip Enable, active Low. This input must be asserted to read data from or  
write data to the HY29LV400. When High, the data bus is tri-stated and the  
device is placed in the Standby mode.  
CE#  
OE#  
WE#  
Input  
Input  
Input  
Output Enable, active Low. Asserted for read operations and negated for  
write operations. BYTE# determines whether a byte or a word is read during the  
read operation.  
Write Enable, active Low. Controls writing of commands or command  
sequences inorder to program data or erase sectors of the memoryarray. A write  
operation takes place when WE# is asserted while CE# is Low and OE# is High.  
Hardware Reset, active Low. Provides a hardware method of resetting the  
HY29LV400 to the read array state. When the device is reset, it immediately  
terminates any operation in progress. While RESET# is asserted, the device  
will be in the Standby mode.  
RESET#  
RY/BY#  
Input  
Ready/Busy Status. Indicates whether a write or erase command is in  
progress or has been completed. Remains Low while the device is actively  
programming data or erasing, and goes High when it is ready to read array data.  
Output  
Open Drain  
3-volt (nominal) power supply.  
Power and signal ground.  
VCC  
VSS  
--  
--  
Rev. 1.0/Nov. 01  
3
HY29LV400  
PIN CONFIGURATIONS  
48-Ball FBGA (6 x 8 mm, Top View, Balls Facing Down)  
H6  
A6  
B6  
C6  
D6  
E6  
F6  
G6  
A[13]  
A[12]  
A[14]  
A[15]  
A[16]  
BYTE#  
DQ[15]/A[-1]  
VSS  
A5  
B5  
C5  
D5  
E5  
F5  
G5  
H5  
A[9]  
A[8]  
A[10]  
A[11]  
DQ[7]  
DQ[14]  
DQ[13]  
DQ[6]  
D4  
NC  
A4  
B4  
C4  
NC  
E4  
F4  
G4  
VCC  
H4  
WE#  
RESET#  
DQ[5]  
DQ[12]  
DQ[4]  
D3  
NC  
A3  
B3  
NC  
C3  
NC  
E3  
F3  
G3  
H3  
RY/BY#  
DQ[2]  
DQ[10]  
DQ[11]  
DQ[3]  
A2  
B2  
C2  
D2  
E2  
F2  
G2  
H2  
A[7]  
A[17]  
A[6]  
A[5]  
DQ[0]  
DQ[8]  
DQ[9]  
DQ[1]  
H1  
A1  
B1  
C1  
D1  
E1  
F1  
G1  
A[3]  
A[4]  
A[2]  
A[1]  
A[0]  
CE#  
OE#  
V SS  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
1
2
3
4
5
6
7
48  
47  
46  
45  
44  
43  
42  
A16  
BYTE#  
VSS  
DQ15/A-1  
DQ7  
DQ14  
DQ6  
A8  
NC  
8
9
41  
40  
DQ13  
DQ5  
NC  
10  
11  
39  
38  
DQ12  
DQ4  
WE#  
RESET#  
NC  
12  
13  
37  
36  
VC C  
DQ11  
TSOP48  
NC  
RY/BY#  
NC  
14  
15  
16  
17  
18  
19  
20  
35  
34  
33  
32  
31  
30  
29  
DQ3  
DQ10  
DQ2  
DQ9  
DQ1  
DQ8  
DQ0  
A17  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
21  
22  
23  
24  
28  
27  
26  
25  
OE#  
VSS  
CE#  
A0  
Rev. 1.0/Nov. 01  
4
HY29LV400  
CONVENTIONS  
Unless otherwise noted, a positive logic (active  
High) convention is assumed throughout this docu-  
ment, whereby the presence at a pin of a higher,  
more positive voltage (VIH) causes assertion of the  
signal. A #symbol following the signal name, e.g.,  
RESET#, indicates that the signal is asserted in  
the Low state (VIL). See DC specifications for VIH  
and VIL values.  
Whenever a signal is separated into numbered  
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of  
bits may also be shown collectively, e.g., as  
DQ[7:0].  
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .  
. . , E, F) indicates a number expressed in hexadeci-  
mal notation. The designation 0bXXXX indicates a  
number expressed in binary notation (X = 0, 1).  
MEMORY ARRAY ORGANIZATION  
Kbytes (4 to 16 Kwords), while the remaining  
seven sectors are uniformly sized at 64 Kbytes  
(32 Kwords). The boot block can be located at  
the bottom of the address range (HY29LV400B)  
or at the top of the address range (HY29LV400T).  
The 4 Mbit Flash memory array is organized into  
eleven blocks called sectors (S0, S1, . . . , S10).  
A sector is the smallest unit that can be erased  
and that can be protected to prevent accidental or  
unauthorized erasure. See the Bus Operations’  
and Command Definitionssections of this docu-  
ment for additional information on these functions.  
Tables 1 and 2 define the sector addresses and  
corresponding address ranges for the top and bot-  
tom boot block versions of the HY29LV400.  
In the HY29LV400, four of the sectors, which com-  
prise the boot block, vary in size from 8 to 32  
BUS OPERATIONS  
ware reset to ensure that no spurious alteration of  
the memory content occurs during the power tran-  
sition. No command is necessary in this mode to  
obtain array data, and the device remains enabled  
for read accesses until the command register con-  
tents are altered.  
Device bus operations are initiated through the  
internal command register, which consists of sets  
of latches that store the commands, along with  
the address and data information, if any, needed  
to execute the specific command. The command  
register itself does not occupy any addressable  
memory location. The contents of the command  
register serve as inputs to an internal state ma-  
chine whose outputs control the operation of the  
device. Table 3 lists the normal bus operations,  
the inputs and control levels they require, and the  
resulting outputs. Certain bus operations require  
a high voltage on one or more device pins. Those  
are described in Table 4.  
This device features an Erase Suspend mode.  
While in this mode, the host may read the array  
data from any sector of memory that is not marked  
for erasure. If the host reads from an address  
within an erase-suspended (or erasing) sector, or  
while the device is performing a byte or word pro-  
gram operation, the device outputs status data  
instead of array data. After completing an Auto-  
matic Program or Automatic Erase algorithm within  
a sector, that sector automatically returns to the  
read array data mode. After completing a program-  
ming operation in the Erase Suspend mode, the  
system may once again read array data with the  
same exception noted above.  
Read Operation  
Data is read from the HY29LV400 by using stan-  
dard microprocessor read cycles while placing the  
byte or word address on the devices address in-  
puts. The host system must drive the CE# and  
OE# pins LOW and drive WE# high for a valid read  
operation to take place. The BYTE# pin determines  
whether the device outputs array data in words  
(DQ[15:0]) or in bytes (DQ[7:0]).  
The host must issue a hardware reset or the soft-  
ware reset command to return a sector to the read  
array data mode if DQ[5] goes high during a pro-  
gram or erase cycle, or to return the device to the  
read array data mode while it is in the Electronic  
ID mode.  
The HY29LV400 is automatically set for reading  
array data after device power-up and after a hard-  
Rev. 1.0/Nov. 01  
5
HY29LV400  
Table 1. HY29LV400T (Top Boot Block) Memory Array Organization  
Sector Address 1  
Size  
Byte Mode  
Word Mode  
Sector  
(KB/KW)  
Address Range 2, 3  
Address Range 2, 3  
A[17] A[16] A[15] A[14] A[13] A[12]  
S0  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
S8  
S9  
S10  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
32/16  
8/4  
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
0x00000 - 0x0FFFF  
0x10000 - 0x1FFFF  
0x20000 - 0x2FFFF  
0x30000 - 0x3FFFF  
0x40000 - 0x4FFFF  
0x50000 - 0x5FFFF  
0x60000 - 0x6FFFF  
0x70000 - 0x77FFF  
0x78000 - 0x79FFF  
0x7A000 - 0x7BFFF  
0x7C000 - 0x7FFFF  
0x00000 - 0x07FFF  
0x08000 - 0x0FFFF  
0x10000 - 0x17FFF  
0x18000 - 0x1FFFF  
0x20000 - 0x27FFF  
0x28000 - 0x2FFFF  
0x30000 - 0x37FFF  
0x38000 - 0x3BFFF  
0x3C000 - 0x3CFFF  
0X3D000 - 0x3DFFF  
0x3E000 - 0x3FFFF  
1
8/4  
1
0
1
16/8  
1
1
X
Notes:  
1. Xindicates dont care.  
2. 0xN. . . Nindicates an address in hexadecimal notation.  
3. The address range in byte mode is A[17:0, -1]. The address range in word mode is A[17:0].  
Table 2. HY29LV400B (Bottom Boot Block) Memory Array Organization  
Sector Address 1  
Size  
Byte Mode  
Word Mode  
Sector  
(KB/KW)  
Address Range 2, 3  
Address Range 2, 3  
A[17] A[16] A[15] A[14] A[13] A[12]  
S0  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
S8  
S9  
S10  
16/8  
8/4  
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
X
0
0x00000 - 0x03FFF  
0x04000 - 0x05FFF  
0x06000 - 0x07FFF  
0x08000 - 0x0FFFF  
0x10000 - 0x1FFFF  
0x20000 - 0x2FFFF  
0x30000 - 0x3FFFF  
0x40000 - 0x4FFFF  
0x50000 - 0x5FFFF  
0x60000 - 0x6FFFF  
0x70000 - 0x7FFFF  
0x00000 - 0x01FFF  
0x02000 - 0x02FFF  
0X03000 - 0x03FFF  
0x04000 - 0x07FFF  
0x08000 - 0x0FFFF  
0x10000 - 0x17FFF  
0x18000 - 0x1FFFF  
0x20000 - 0x27FFF  
0x28000 - 0x2FFFF  
0x30000 - 0x37FFF  
0x38000 - 0x3FFFF  
8/4  
0
1
1
32/16  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
64/32  
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes:  
1. Xindicates dont care.  
2. 0xN. . . Nindicates an address in hexadecimal notation.  
3. The address range in byte mode is A[17:0, -1]. The address range in word mode is A[17:0].  
Rev. 1.0/Nov. 01  
6
HY29LV400  
Table 3. HY29LV400 Normal Bus Operations 1  
DQ[15:8]3  
BYTE# = H BYTE# = L  
Operation  
CE#  
OE#  
WE#  
RESET# Address 2 DQ[7:0]  
Read  
Write  
L
L
L
H
H
X
X
H
L
H
AIN  
AIN  
X
DOUT  
DIN  
DOUT  
DIN  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
H
Output Disable  
L
H
X
X
H
H
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
CE# Normal Standby  
H
X
CE# Deep Standby VCC ± 0.3V  
VCC ± 0.3V  
X
Hardware Reset  
X
X
X
X
X
L
X
X
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
(Normal Standby)  
Hardware Reset  
X
VSS ± 0.3V  
(Deep Standby)  
Notes:  
1. L = VIL, H = VIH, X = Dont Care (L or H), DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.  
2. Address is A[17:0, -1] in Byte Mode and A[17:0] in Word Mode.  
3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).  
Table 4. HY29LV400 Bus Operations Requiring High Voltage1, 2  
DQ[15:8]  
Operation 3  
CE# OE# WE# RESET# A[19:12] A[9] A[6] A[1] A[0] DQ[7:0]  
BYTE# BYTE#  
= H  
= L 5  
X
Sector Protect  
L
L
H
H
L
L
VID  
VID  
SA 4  
X
X
X
L
H
H
L
L
DIN/DOUT  
DIN/DOUT  
X
Sector Unprotect  
Temporary Sector  
H
X
X
--  
L
--  
L
--  
VID  
H
--  
X
--  
--  
L
--  
L
--  
L
--  
--  
X
--  
6
Unprotect  
Manufacturer Code  
H
VID  
0xAD  
0xBA  
0xB9  
High-Z  
HY29LV400B  
Device  
L
L
H
H
X
VID  
L
L
H
0x22 High-Z  
Code  
HY29LV400T  
0x00 =  
Unprotected  
Sector Protection  
Verification  
L
L
H
H
SA 4  
VID  
L
H
L
X
High-Z  
0x01 =  
Protected  
Notes:  
1. L = VIL, H = VIH, X = Dont Care (L OR H). See DC Characteristics for voltage levels.  
2. Address bits not specified are Dont Care.  
3. See text and for additional information.  
4. SA = Sector Address. See Tables 1 and 2.  
5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).  
6. Normal read, write and output disable operations are used in this mode. See Table 3.  
Rev. 1.0/Nov. 01  
7
HY29LV400  
entered when addresses remain stable for tACC  
+
Write Operation  
30 ns (typical) and is independent of the state of  
the CE#, WE#, and OE# control signals. Stan-  
dard address access timings provide new data  
when addresses are changed. While in sleep  
mode, output data is latched and always available  
to the system.  
Certain operations, including programming data  
and erasing sectors of memory, require the host  
to write a command or command sequence to the  
HY29LV400. Writes to the device are performed  
by placing the byte or word address on the devices  
address inputs while the data to be written is input  
on DQ[15:0] (BYTE# = High) or DQ[7:0] (BYTE#  
= Low). The host system must drive the CE# and  
WE# pins Low and drive OE# High for a valid write  
operation to take place. All addresses are latched  
on the falling edge of WE# or CE#, whichever hap-  
pens later. All data is latched on the rising edge of  
WE# or CE#, whichever happens first.  
NOTE: Sleep mode is entered only when the device is  
in Read mode. It is not entered if the device is executing  
an automatic algorithm, if it is in Erase Suspend mode,  
or during receipt of a command sequence.  
Output Disable Operation  
When the OE# input is at VIH, output data from the  
device is disabled and the data bus pins are placed  
in the high impedance state.  
The Device Commandssection of this data sheet  
provides details on the specific device commands  
implemented in the HY29LV400.  
Reset Operation  
The RESET# pin provides a hardware method of  
resetting the device to reading array data. When  
the RESET# pin is driven low for the minimum  
specified period, the device immediately termi-  
nates any operation in progress, tri-states the data  
bus pins, and ignores all read/write commands for  
the duration of the RESET# pulse. The device also  
resets the internal state machine to reading array  
data. If an operation was interrupted by the as-  
sertion of RESET#, it should be reinitiated once  
the device is ready to accept another command  
sequence to ensure data integrity.  
Standby Operation  
When the system is not reading or writing to the  
device, it can place the HY29LV400 in the Standby  
mode. In this mode, current consumption is greatly  
reduced, and the data bus outputs are placed in  
the high impedance state, independent of the OE#  
input. The Standby mode can be invoked using  
two methods.  
The device enters the CE# Deep Standby mode  
when the CE# and RESET# pins are both held at  
VCC ± 0.3V. Note that this is a more restricted volt-  
age range than VIH . If both CE# and RESET# are  
held at VIH, but not within VCC ± 0.3V, the device  
will be in the CE# Normal Standby mode, but the  
standby current will be greater.  
Current is reduced for the duration of the RESET#  
pulse as described in the Standby Operation sec-  
tion above.  
If RESET# is asserted during a program or erase  
operation, the RY/BY# pin remains Low (busy) until  
the internal reset operation is complete, which re-  
quires a time of tREADY (during Automatic Algo-  
rithms). The system can thus monitor RY/BY# to  
determine when the reset operation completes,  
and can perform a read or write operation tRB after  
RY/BY# goes High. If RESET# is asserted when  
a program or erase operation is not executing (RY/  
BY# pin is High), the reset operation is completed  
within a time of tRP. In this case, the host can per-  
form a read or write operation tRH after the RE-  
SET# pin returns High .  
The device enters the RESET# Deep Standby  
mode when the RESET# pin is held at VSS ± 0.3V.  
If RESET# is held at VIL but not within VSS ± 0.3V,  
the device will be in the RESET# Normal Standby  
mode, but the standby current will be greater. See  
Reset Operation for additional information.  
The device requires standard access time (tCE) for  
read access when the device is in either of the  
standby modes, before it is ready to read data.  
Note: If the device is deselected during an erase or  
programming operation, it continues to draw active  
current until the operation is completed.  
The RESET# pin may be tied to the system reset  
signal. Thus, a system reset would also reset the  
device, enabling the system to read the boot-up  
firmware from the Flash memory.  
Sleep Mode  
The sleep mode automatically minimizes device  
power consumption. This mode is automatically  
Rev. 1.0/Nov. 01  
8
HY29LV400  
Sector Protect Operation  
protection must be protected again after the un-  
protect procedure is run.  
The hardware sector protection feature disables  
both program and erase operations in any sector  
or combination of sectors. This function can be  
implemented either in-system or by using program-  
ming equipment.  
The Sector Unprotect procedure requires VID on  
the RESET# pin and uses standard microproces-  
sor bus cycle timing to implement sector unpro-  
tection. The flow chart in Figure 2 illustrates the  
algorithm.  
The Sector Protect procedure requires VID on the  
RESET# pin and uses standard microprocessor  
bus cycle timing to implement sector protection.  
The flow chart in Figure 1 illustrates the algorithm.  
Temporary Sector Unprotect Operation  
This feature allows temporary unprotection of pre-  
viously protected sectors to allow changing the  
data in-system. Sector Unprotect mode is activated  
by setting the RESET# pin to VID. While in this  
mode, formerly protected sectors can be pro-  
grammed or erased by invoking the appropriate  
commands (see Device Commands section).  
Once VID is removed from RESET#, all the previ-  
ously protected sectors are protected again. Fig-  
ure 3 illustrates the algorithm.  
The HY29LV400 is shipped with all sectors un-  
protected. It is possible to determine whether a  
sector is protected or unprotected. See the Elec-  
tronic ID Mode section for details.  
Sector Unprotect Operation  
The hardware sector unprotection feature re-en-  
ables both program and erase operations in pre-  
viously protected sectors. This function can be  
implemented either in-system or by using program-  
ming equipment. Note that to unprotect any sec-  
tor, all unprotected sectors must first be protected  
prior to the first sector unprotect write cycle. Also,  
the unprotect procedure will cause all sectors to  
become unprotected, thus, sectors that require  
Electronic ID Operation (High Voltage Method)  
The Electronic ID mode provides manufacturer and  
device identification and sector protection verifi-  
cation through codes output on DQ[15:0]. This  
mode is intended primarily for programming equip-  
ment to automatically match a device to be pro-  
START  
Wait 150 us  
RESET# = VIH  
RESET# = VID  
Write 0x40 to Address  
Write Reset Command  
Wait 1 us  
Read from Address  
SECTOR PROTECT  
COMPLETE  
Write 0x60 to device  
NO  
YES  
Data = 0x01?  
TRYCNT = 25?  
TRYCNT = 1  
NO  
YES  
Increment TRYCNT  
Set Address:  
A[17:12] = Sector to Protect  
A[6] = 0, A[1] = 1, A[0] = 0  
Protect Another  
DEVICE FAILURE  
NO  
Sector?  
Write 0x60 to Address  
YES  
Figure 1. Sector Protect Algorithm  
Rev. 1.0/Nov. 01  
9
HY29LV400  
START  
(Note: All sectors must be  
protected prior to  
unprotecting any sector)  
Set Address:  
A[17:12] = Sector SNUM  
A[6] = 1, A]1] = 1, A]0] = 0  
RESET# = VIH  
TRYCNT = 1  
SNUM = 0  
Write Reset Command  
Write 0x40 to Address  
Read from Address  
SECTOR UNPROTECT  
COMPLETE  
RESET# = VID  
Wait 1 us  
NO  
YES  
Data = 0x00?  
TRYCNT = 1000?  
Write 0x60 to device  
NO  
YES  
Set Address:  
A[6] = 1, A]1] = 1, A]0] = 0  
Increment TRYCNT  
YES  
DEVICE FAILURE  
SNUM = 10?  
Write 0x60 to Address  
Wait 15 ms  
NO  
SNUM = SNUM + 1  
Figure 2. Sector Unprotect Algorithm  
grammed with its corresponding programming al-  
gorithm.  
START  
Two methods are provided for accessing the Elec-  
tronic ID data. The first requires VID on address  
pin A[9], with additional requirements for obtain-  
ing specific data items listed in Table 4. The Elec-  
tronic ID data can also be obtained by the host  
through specific commands issued via the com-  
mand register, as described in the Device Com-  
mandssection of this data sheet.  
RESET# = VID  
(All protected sectors  
become unprotected)  
Perform Program or Erase  
Operations  
RESET# = VIH  
(All previously protected  
sectors return to protected  
state)  
While in the high-voltage Electronic ID mode, the  
system may read at specific addresses to obtain  
certain device identification and status information:  
n A read cycle at address 0xXXX00 retrieves the  
TEMPORARY SECTOR  
UNPROTECT COMPLETE  
manufacturer code.  
n A read cycle at address 0xXXX01 in Word  
mode or 0xXXX02 in Byte mode returns the  
device code.  
Figure 3. Temporary Sector Unprotect  
Algorithm  
n A read cycle containing a sector address (SA)  
in A[17:12] and the address 0x02 in Word mode  
or 0x04 in Byte mode, returns 0x01 if that sec-  
tor is protected, or 0x00 if it is unprotected.  
Rev. 1.0/Nov. 01  
10  
HY29LV400  
DEVICE COMMANDS  
Table 5. Composition of Command Sequences  
Device operations are initiated by writing desig-  
nated address and data command sequences into  
the device. Addresses are latched on the falling  
edge of WE# or CE#, whichever happens later.  
Data is latched on the rising edge of WE# or CE#,  
whichever happens first.  
Number of Bus Cycles  
Command  
Sequence  
Unlock Command  
Data  
Reset  
Read  
0
0
2
2
1
0
1
1
0
Note 1  
Byte/Word Program  
Unlock Bypass  
1
0
A command sequence is composed of one, two  
or three of the following sub-segments: an unlock  
cycle, a command cycle and a data cycle. Table 5  
summarizes the composition of the valid command  
sequences implemented in the HY29LV400, and  
these sequences are fully described in Table 6 and  
in the sections that follow.  
Unlock Bypass  
Reset  
Unlock Bypass  
Byte/Word Program  
0
0
1
1
1
1
Chip Erase  
Sector Erase  
Erase Suspend  
Erase Resume  
4
4
0
0
2
1
1
1
1
1
1
Writing incorrect address and data values or writ-  
ing them in the improper sequence resets the  
HY29LV400 to the Read mode.  
1 (Note 2)  
0
0
Reading Data  
Electronic ID  
Note 3  
The device automatically enters the Read mode  
after device power-up, after the RESET# input is  
asserted and upon the completion of certain com-  
mands. Commands are not required to retrieve  
data in this mode. See Read Operation section  
for additional information.  
Notes:  
1. Any number of Flash array read cycles are permitted.  
2. Additional data cycles may follow. See text.  
3. Any number of Electronic ID read cycles are permitted.  
the Read mode (or to the Erase Suspend mode  
if the device was in Erase Suspend when the  
Program command was issued).  
Reset Command  
The Reset command may also be used to abort  
certain command sequences:  
Writing the Reset command resets the sectors to  
the Read or Erase-Suspend mode. Address bits  
are dont cares for this command.  
n In a Sector Erase or Chip Erase command se-  
quence, the Reset command may be written  
at any time before erasing actually begins, in-  
cluding, for the Sector Erase command, be-  
tween the cycles that specify the sectors to be  
erased (see Sector Erase command descrip-  
tion). This aborts the command and resets the  
device to the Read mode. Once erasure be-  
gins, however, the device ignores the Reset  
command until the operation is complete.  
As described above, a Reset command is not nor-  
mally required to begin reading array data. How-  
ever, a Reset command must be issued in order  
to read array data in the following cases:  
n If the device is in the Electronic ID mode, a  
Reset command must be written to return to  
the Read mode. If the device was in the Erase  
Suspend mode when the device entered the  
Electronic ID mode, writing the Reset command  
returns the device to the Erase Suspend mode.  
n In a Program command sequence, the Reset  
command may be written between the se-  
quence cycles before programming actually be-  
gins. This aborts the command and resets the  
device to the Read mode, or to the Erase Sus-  
pend mode if the Program command sequence  
is written while the device is in the Erase Sus-  
pend mode. Once programming begins, how-  
ever, the device ignores the Reset command  
until the operation is complete.  
Note: When in the Electronic ID bus operation mode,  
the device returns to the Read mode when VID is removed  
from the A[9] pin. The Reset command is not required  
in this case.  
n If DQ[5] (Exceeded Time Limit) goes High dur-  
ing a program or erase operation, a Reset com-  
mand must be invoked to return the sectors to  
Rev. 1.0/Nov. 01  
11  
HY29LV400  
E l e c t r o n i c I D  
6
Rev. 1.0/Nov. 01  
12  
HY29LV400  
Notes for Table 6:  
1. All values are in hexadecimal. DQ[15:8] are dont care for unlock and command cycles.  
2. All bus cycles are write operations unless otherwise noted.  
3. Address is A[10:0] in Word mode and A[10:0, -1] in Byte mode. A[17:11] are dont care except as follows:  
?
?
?
For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed.  
For the sixth cycle of Sector Erase, SA = A[17:12] are the sector address of the sector to be erased.  
For the fourth cycle of Sector Protect Verify, SA = A[17:12] are the sector address of the sector to be verified.  
4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-  
erasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode.  
5. The Erase Resume command is valid only during the Erase Suspend mode.  
6. The fourth bus cycle is a read cycle.  
7. The command is required only to return to the Read mode when the device is in the Electronic ID command mode. It must  
also be issued to return to read mode if DQ[5] goes High during a program or erase operation. It is not required for normal  
read operations.  
8. The Unlock Bypass command is required prior to the Unlock Bypass Program command.  
n The Reset command may be written between  
the cycles in an Electronic ID command se-  
quence to abort that command. As described  
above, once in the Electronic ID mode, the  
Reset command must be written to return to  
the array Read mode.  
to a 1. Attempting to do so may halt the opera-  
tion and set DQ[5] to 1, or cause the Data# Poll-  
ing algorithm to indicate the operation was suc-  
cessful. However, a succeeding read will show  
that the data is still 0.  
Figure 4 illustrates the programming procedure.  
Program Command  
Unlock Bypass/Bypass Program/Bypass Reset  
Commands  
The system programs the device a word or byte  
at a time by issuing the appropriate four-cycle pro-  
gram command sequence as shown in Table 6.  
The sequence begins by writing two unlock cycles,  
followed by the program setup command and,  
lastly, the program address and data. This ini-  
tiates the Automatic Program algorithm which au-  
tomatically provides internally generated program  
pulses and verifies the programmed cell margin.  
The host is not required to provide further con-  
trols or timings during this operation. When the  
Automatic Program algorithm is complete, the de-  
vice returns to the array Read mode (or to the  
Erase Suspend mode if the device was in Erase  
Suspend when the Program command was is-  
sued). Several methods are provided to allow the  
host to determine the status of the programming  
operation, as described in the Write Operation  
Status section.  
Unlock bypass provides a faster method for the  
host system to program the device. As shown in  
Table 6, the Unlock Bypass command sequence  
consists of two unlock write cycles followed by a  
third write cycle containing the Unlock Bypass  
command, 0x20. In the Unlock Bypass mode, a  
two-cycle Unlock Bypass Program command se-  
quence is used instead of the standard four-cycle  
Program sequence to invoke a programming op-  
eration. The first cycle in this sequence contains  
the Unlock Bypass Program command, 0xA0, and  
the second cycle specifies the program address  
and data, thus eliminating the initial two unlock  
cycles required in the standard Program command  
sequence Additional data is programmed in the  
same manner.  
During the Unlock Bypass mode, only the Unlock  
Bypass program and Unlock Bypass Reset com-  
mands are valid. To exit the Unlock Bypass mode,  
the host must issue the two-cycle Unlock Bypass  
Reset command sequence shown in Table 6. The  
device then returns to the array Read mode.  
Commands written to the device during execution  
of the Automatic Program algorithm are ignored.  
Note that a hardware reset immediately terminates  
the programming operation. To ensure data in-  
tegrity, the aborted Program command sequence  
should be reinitiated once the reset operation is  
complete.  
Chip Erase Command  
The Chip Erase command sequence consists of  
two unlock cycles, followed by a set-up command,  
two additional unlock cycles and then the Chip  
Erase command. This sequence invokes the Au-  
Programming is allowed in any sequence. Only  
erase operations can convert a stored 0to a 1.  
Thus, a bit cannot be programmed from a 0back  
Rev. 1.0/Nov. 01  
13  
HY29LV400  
START  
Check Programming Status  
(See Write Operation Status  
Section)  
DQ[5] Error Exit  
NO  
Enable Fast  
Programming Verified  
Programming?  
YES  
NO  
Last Word/Byte  
Done?  
Issue UNLOCK BYPASS  
Command  
YES  
Setup Next Address/Data for  
Program Operation  
NO  
Unlock Bypass  
Mode?  
YES  
NO  
Unlock Bypass  
Mode?  
Issue UNLOCK BYPASS  
RESET Command  
Issue NORMAL PROGRAM  
Command  
YES  
Issue UNLOCK BYPASS  
PROGRAM Command  
PROGRAMMING  
COMPLETE  
GO TO ERROR  
RECOVERY PROCEDURE  
Figure 4. Normal and Unlock Bypass Programming Procedures  
tomatic Erase algorithm that automatically  
When the Automatic Erase algorithm is complete,  
the device returns to the array Read mode. Sev-  
eral methods are provided to allow the host to  
determine the status of the erase operation, as  
described in the Write Operation Status section.  
preprograms and verifies the entire memory for  
an all zero data pattern prior to electrical erase.  
The host system is not required to provide any  
controls or timings during these operations.  
Commands written to the device during execution  
of the Automatic Erase algorithm are ignored. Note  
that a hardware reset immediately terminates the  
chip erase operation. To ensure data integrity, the  
aborted Chip Erase command sequence should  
be reissued once the reset operation is complete.  
Figure 5 illustrates the chip erase procedure.  
Sector Erase Command  
The Sector Erase command sequence consists  
of two unlock cycles, followed by the Erase com-  
mand, two additional unlock cycles and then the  
sector erase data cycle, which specifies the sec-  
tor to be erased. As described later in this sec-  
tion, multiple sectors can be specified for erasure  
with a single command sequence. During sector  
erase, all specified sectors are erased sequen-  
tially. The data in sectors not specified for era-  
sure, as well as the data in any protected sectors,  
even if specified for erasure, is not affected by the  
sector erase operation.  
START  
Issue CHIP ERASE  
Command Sequence  
Check Erase Status  
DQ[5] Error Exit  
(See Write Operation Status  
Section)  
Normal Exit  
The Sector Erase command sequence starts the  
Automatic Erase algorithm, which preprograms  
and verifies the specified unprotected sectors for  
an all zero data pattern prior to electrical erase.  
The device then provides the required number of  
GO TO  
CHIP ERASE COMPLETE  
ERROR RECOVERY  
Figure 5. Chip Erase Procedure  
14  
Rev. 1.0/Nov. 01  
HY29LV400  
internally generated erase pulses and verifies cell  
erasure within the proper cell margins. The host  
system is not required to provide any controls or  
timings during these operations.  
the unprotected sectors, and ignores the command  
for the sectors that are protected.  
The system can monitor DQ[3] to determine if the  
50 μs sector erase time-out has expired, as de-  
scribed in the Write Operation Status section. If  
the time between additional sector erase data  
cycles can be insured to be less than the time-  
out, the system need not monitor DQ[3].  
After the sector erase data cycle (the sixth bus  
cycle) of the command sequence is issued, a sec-  
tor erase time-out of 50 μs (min), measured from  
the rising edge of the final WE# pulse in that bus  
cycle, begins. During this time-out window, an ad-  
ditional sector erase data cycle, specifying the  
sector address of another sector to be erased, may  
be written into an internal sector erase buffer. This  
buffer may be loaded in any sequence, and the  
number of sectors specified may be from one sec-  
tor to all sectors. The only restriction is that the  
time between these additional data cycles must  
be less than 50 μs, otherwise erasure may begin  
before the last data cycle is accepted. To ensure  
that all data cycles are accepted, it is recom-  
mended that host processor interrupts be disabled  
during the time that the additional cycles are be-  
ing issued and then be re-enabled afterwards.  
Any command other than Sector Erase or Erase  
Suspend during the time-out period resets the  
device to reading array data. The system must  
then rewrite the command sequence, including any  
additional sector erase data cycles. Once the sec-  
tor erase operation itself has begun, only the Erase  
Suspend command is valid. All other commands  
are ignored.  
As for the Chip Erase command, note that a hard-  
ware reset immediately terminates the sector  
erase operation. To ensure data integrity, the  
aborted Sector Erase command sequence should  
be reissued once the reset operation is complete.  
When the Automatic Erase algorithm terminates,  
the device returns to the array Read mode. Sev-  
eral methods are provided to allow the host to de-  
termine the status of the erase operation, as de-  
scribed in the Write Operation Status section.  
If all sectors specified for erasing are protected,  
the device returns to reading array data after ap-  
proximately 100 μs. If at least one specified sec-  
tor is not protected, the erase operation erases  
START  
Check Erase Status  
DQ[5] Error Exit  
(See Write Operation Status  
Section)  
Normal Exit  
Write First Five Cycles of  
SECTOR ERASE  
Command Sequence  
GO TO  
ERASE COMPLETE  
ERROR RECOVERY  
Setup First (or Next) Sector  
Address for Erase Operation  
Write Last Cycle (SA/0x30)  
of SECTOR ERASE  
Command Sequence  
Sectors which require erasure  
but which were not specified in  
this erase cycle must be erased  
later using a new command  
sequence  
NO  
Sector Erase  
Time-out (DQ[3])  
Expired?  
Erase An  
Additional Sector?  
YES  
YES  
NO  
Figure 6. Sector Erase Procedure  
Rev. 1.0/Nov. 01  
15  
HY29LV400  
The system must write the Erase Resume com-  
mand to exit the Erase Suspend mode and con-  
tinue the sector erase operation. Further writes of  
the Resume command are ignored. Another Erase  
Suspend command can be written after the de-  
vice has resumed erasing.  
Figure 6 illustrates the Sector Erase procedure.  
Erase Suspend/Erase Resume Commands  
The Erase Suspend command allows the system  
to interrupt a sector erase operation to read data  
from, or program data in, any sector not being  
erased. The command causes the erase opera-  
tion to be suspended in all sectors specified for  
erasure. This command is valid only during the  
sector erase operation, including during the 50 μs  
time-out period at the end of the command se-  
quence, and is ignored if it is issued during chip  
erase or programming operations.  
Electronic ID Command  
The Electronic ID mode provides manufacturer and  
device identification and sector protection verifi-  
cation through identifier codes output on DQ[7:0].  
This mode is intended primarily for programming  
equipment to automatically match a device to be  
programmed with its corresponding programming  
algorithm.  
The HY29LV400 requires a maximum of 20 μs to  
suspend the erase operation if the Erase Suspend  
command is issued during sector erasure. How-  
ever, if the command is written during the time-  
out, the time-out is terminated and the erase op-  
eration is suspended immediately. Once the erase  
operation has been suspended, the system can  
read array data from or program data to any sec-  
tor not specified for erasure. Normal read and  
write timings and command definitions apply.  
Reading at any address within erase-suspended  
sectors produces status data on DQ[7:0]. The host  
can use DQ[7], or DQ[6] and DQ[2] together, to  
determine if a sector is actively erasing or is erase-  
suspended. See the Write Operation Status sec-  
tion for information on these status bits.  
Two methods are provided for accessing the Elec-  
tronic ID data. The first requires VID on address  
pin A[9], as described previously in the Device  
Operations section.  
The Electronic ID data can also be obtained by  
the host by invoking the Electronic ID command,  
as shown in Table 6. This method does not re-  
quire VID. The Electronic ID command sequence  
may be issued while the device is in the Read  
mode or in the Erase Suspend Read mode, that  
is, except while programming or erasing.  
The Electronic ID command sequence is initiated  
by writing two unlock cycles, followed by the Elec-  
tronic ID command. The device then enters the  
Electronic ID mode, and the system may read at  
any address any number of times, without initiat-  
ing another command sequence.  
After an erase-suspended program operation is  
complete, the host can initiate another program-  
ming operation (or read operation) within non-sus-  
pended sectors. The host can determine the sta-  
tus of a program operation during the Erase-Sus-  
pended state just as in the standard programming  
operation.  
n A read cycle at address 0xXXX00 retrieves the  
manufacturer code.  
n A read cycle at address 0xXXX01 in Word  
mode or 0xXXX02 in Byte mode returns the  
device code.  
The host may also write the Electronic ID com-  
mand sequence when the device is in the Erase  
Suspend mode. The device allows reading Elec-  
tronic ID codes even at addresses within erasing  
sectors, since the codes are not stored in the  
memory array. When the device exits the Elec-  
tronic ID mode, the device reverts to the Erase  
Suspend mode, and is ready for another valid op-  
eration. See Electronic ID Mode section for more  
information.  
n A read cycle containing a sector address (SA)  
in A[17:12] and the address 0x02 in A[7:0] in  
Word mode (or 0x04 in A[6:0, -1] in Byte mode)  
returns 0x01 if that sector is protected, or 0x00  
if it is unprotected.  
The system must write the Reset command to exit  
the Electronic ID mode and return to reading ar-  
ray data.  
Rev. 1.0/Nov. 01  
16  
HY29LV400  
Table 7. Write and Erase Operation Status Summary  
1
1
Mode  
Operation  
Programming in progress  
Programming completed  
Erase in progress  
DQ[7]  
DQ[7]#  
Data  
0
DQ[6]  
Toggle  
Data 4  
Toggle  
Data 4  
DQ[5]  
0/1 2  
DQ[3]  
N/A  
DQ[2]  
N/A  
RY/BY#  
0
1
Data  
0/1 2  
Data  
1 3  
Data  
Normal  
Toggle  
Data 4  
0
1
Erase completed 5  
Data  
Data  
Data  
Read within erase suspended  
sector  
1
No toggle  
Data  
0
N/A  
Toggle  
Data  
1
1
Read within non-erase  
suspended sector  
Erase  
Data  
Data  
Data  
Suspend  
Programming in progress 6  
Programming completed 6  
DQ[7]#  
Data  
Toggle  
Data 4  
0/1 2  
N/A  
N/A  
0
1
Data  
Data  
Data  
Notes:  
1. A valid address is required when reading status information. See text for additional information.  
2. DQ[5] status switches to a 1when a program or erase operation exceeds the maximum timing limit.  
3. A 1during sector erase indicates that the 50 μs time-out has expired and active erasure is in progress. DQ[3] is not  
applicable to the chip erase operation.  
4. Equivalent to No Togglebecause data is obtained in this state.  
5. Data (DQ[7:0]) = 0xFF immediately after erasure.  
6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).  
WRITE OPERATION STATUS  
rithm is in progress or completed, or whether the  
device is in Erase Suspend mode. Data# Polling  
is valid after the rising edge of the final WE# pulse  
in the Program or Erase command sequence.  
The HY29LV400 provides a number of facilities to  
determine the status of a program or erase op-  
eration. These are the RY/BY# (Ready/Busy#)  
pin and certain bits of a status word which can be  
read from the device during the programming and  
erase operations. Table 7 summarizes the status  
indications and further detail is provided in the  
subsections which follow.  
The system must do a read at the program ad-  
dress to obtain valid programming status informa-  
tion on this bit. While a programming operation is  
in progress, the device outputs the complement  
of the value programmed to DQ[7]. When the pro-  
gramming operation is complete, the device out-  
puts the value programmed to DQ[7]. If a pro-  
gram operation is attempted within a protected  
sector, Data# Polling on DQ[7] is active for ap-  
proximately 1 μs, then the device returns to read-  
ing array data.  
RY/BY# - Ready/Busy#  
RY/BY# is an open-drain output pin that indicates  
whether a programming or erase Automatic Algo-  
rithm is in progress or has completed. A pull-up  
resistor to VCC is required for proper operation. RY/  
BY# is valid after the rising edge of the final WE#  
pulse in the corresponding command sequence.  
The host must read at an address within any non-  
protected sector specified for erasure to obtain  
valid erase status information on DQ[7]. During  
an erase operation, Data# Polling produces a 0”  
on DQ[7]. When the erase operation is complete,  
or if the device enters the Erase Suspend mode,  
Data# Polling produces a 1on DQ[7]. If all sec-  
tors selected for erasing are protected, Data#  
Polling on DQ[7] is active for approximately 100  
μs, then the device returns to reading array data.  
If at least one selected sector is not protected, the  
erase operation erases the unprotected sectors,  
If the output is Low (busy), the device is actively  
erasing or programming, including programming  
while in the Erase Suspend mode. If the output is  
High (ready), the device has completed the op-  
eration and is ready to read array data in the nor-  
mal or Erase Suspend modes, or it is in the  
Standby mode.  
DQ[7] - Data# Polling  
The Data# (Data Bar) Polling bit, DQ[7], indicates  
to the host system whether an Automatic Algo-  
Rev. 1.0/Nov. 01  
17  
HY29LV400  
erase time-out. The system may use either OE#  
or CE# to control the read cycles.  
and ignores the command for the specified sec-  
tors that are protected.  
Successive read cycles at any address during an  
Automatic Program algorithm operation (including  
programming while in Erase Suspend mode)  
cause DQ[6] to toggle. DQ[6] stops toggling when  
the operation is complete. If a program address  
falls within a protected sector, DQ[6] toggles for  
approximately one μs after the program command  
sequence is written, then returns to reading array  
data.  
When the system detects that DQ[7] has changed  
from the complement to true data (or 0to 1for  
erase), it should do an additional read cycle to read  
valid data from DQ[7:0]. This is because DQ[7]  
may change asynchronously with respect to the  
other data bits while Output Enable (OE#) is as-  
serted low.  
Figure 7 illustrates the Data# Polling test algorithm.  
While the Automatic Erase algorithm is operating,  
successive read cycles at any address cause  
DQ[6] to toggle. DQ[6] stops toggling when the  
erase operation is complete or when the device is  
placed in the Erase Suspend mode. The host may  
use DQ[2] to determine which sectors are erasing  
or erase-suspended (see below). After an Erase  
command sequence is written, if all sectors se-  
lected for erasing are protected, DQ[6] toggles for  
approximately 100 μs, then returns to reading ar-  
ray data. If at least one selected sector is not pro-  
tected, the Automatic Erase algorithm erases the  
unprotected sectors, and ignores the selected sec-  
tors that are protected.  
DQ[6] - Toggle Bit I  
Toggle Bit I on DQ[6] indicates whether an Auto-  
matic Program or Erase algorithm is in progress  
or complete, or whether the device has entered  
the Erase Suspend mode. Toggle Bit I may be read  
at any address, and is valid after the rising edge  
of the final WE# pulse in the Program or Erase  
command sequence, including during the sector  
START  
Read DQ[7:0]  
at Valid Address (Note 1)  
DQ[2] - Toggle Bit II  
Test for DQ[7] = 1?  
for Erase Operation  
Toggle Bit II, DQ[2], when used with DQ[6], indi-  
cates whether a particular sector is actively eras-  
ing or whether that sector is erase-suspended.  
Toggle Bit II is valid after the rising edge of the  
final WE# pulse in the command sequence. The  
device toggles DQ[2] with each OE# or CE# read  
cycle.  
DQ[7] = Data?  
YES  
NO  
NO  
DQ[5] = 1?  
DQ[2] toggles when the host reads at addresses  
within sectors that have been specified for era-  
sure, but cannot distinguish whether the sector is  
actively erasing or is erase-suspended. DQ[6],  
by comparison, indicates whether the device is ac-  
tively erasing or is in Erase Suspend, but cannot  
distinguish which sectors are specified for erasure.  
Thus, both status bits are required for sector and  
mode information.  
YES  
Read DQ[7:0]  
at Valid Address (Note 1)  
Test for DQ[7] = 1?  
for Erase Operation  
DQ[7] = Data?  
(Note 2)  
YES  
NO  
PROGRAM/ERASE  
EXCEEDED TIME ERROR  
PROGRAM/ERASE  
COMPLETE  
Figure 8 illustrates the operation of Toggle Bits I  
and II.  
Notes:  
1. During programming , the program address. During sector erase , an  
address within any non-protected sector specified for erasure. During  
chip erase , an address within any non-protected sector.  
DQ[5] - Exceeded Timing Limits  
2. Recheck DQ[7] since it may change asynchronously to DQ[5].  
DQ[5] is set to a 1when the program or erase  
time has exceeded a specified internal pulse count  
Figure 7. Data# Polling Test Algorithm  
18  
Rev. 1.0/Nov. 01  
HY29LV400  
START  
DQ[5] = 1?  
YES  
Read DQ[7:0]  
at Valid Address (Note 1)  
NO  
Read DQ[7:0]  
Read DQ[7:0]  
Read DQ[7:0]  
at Valid Address (Note 1)  
Read DQ[7:0]  
at Valid Address (Note 1)  
YES  
NO  
DQ[6] Toggled?  
(Note 2)  
NO  
DQ[6] Toggled?  
DQ[2] Toggled?  
YES  
NO  
(Note 4)  
NO  
(Note 3)  
YES  
PROGRAM/ERASE  
COMPLETE  
PROGRAM/ERASE  
EXCEEDED TIME ERROR  
SECTOR BEING READ  
IS IN ERASE SUSPEND  
SECTOR BEING READ  
IS NOT IN ERASE SUSPEND  
Notes  
:
1. During programming, the program address.  
During sector erase, an address within any sector scheduled for erasure.  
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.  
3. Use this path if testing for Program/Erase status.  
4. Use this path to test whether sector is in Erase Suspend mode.  
Figure 8. Toggle Bit I and II Test Algorithm  
limit. This is a failure condition that indicates that  
the program or erase cycle was not successfully  
completed. DQ[5] status is valid only while DQ[7]  
or DQ[6] indicate that the Automatic Algorithm is  
in progress.  
to a 1. Refer to the Sector Erase Command”  
section for additional information. Note that the  
sector erase timer does not apply to the Chip Erase  
command.  
After the initial Sector Erase command sequence  
is issued, the system should read the status on  
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to  
ensure that the device has accepted the command  
sequence, and then read DQ[3]. If DQ[3] is a 1,  
the internally controlled erase cycle has begun and  
all further sector erase data cycles or commands  
(other than Erase Suspend) are ignored until the  
erase operation is complete. If DQ[3] is a 0, the  
device will accept a sector erase data cycle to mark  
an additional sector for erasure. To ensure that  
the data cycles have been accepted, the system  
software should check the status of DQ[3] prior to  
and following each subsequent sector erase data  
cycle. If DQ[3] is high on the second status check,  
the last data cycle might not have been accepted.  
The DQ[5] failure condition will also be signaled if  
the host tries to program a 1to a location that is  
previously programmed to 0, since only an erase  
operation can change a 0to a 1.  
For both of these conditions, the host must issue  
a Reset command to return the device to the Read  
mode.  
DQ[3] - Sector Erase Timer  
After writing a Sector Erase command sequence,  
the host may read DQ[3] to determine whether or  
not an erase operation has begun. When the  
sector erase time-out expires and the sector erase  
operation commences, DQ[3] switches from a 0’  
Rev. 1.0/Nov. 01  
19  
HY29LV400  
HARDWARE DATA PROTECTION  
The HY29LV400 provides several methods of pro-  
tection to prevent accidental erasure or program-  
ming which might otherwise be caused by spuri-  
ous system level signals during VCC power-up and  
power-down transitions, or from system noise.  
These methods are described in the sections that  
follow.  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#,  
CE# or WE# do not initiate a write cycle.  
Logical Inhibit  
Write cycles are inhibited by asserting any one of  
the following conditions: OE# = VIL , CE# = VIH, or  
WE# = VIH. To initiate a write cycle, CE# and WE#  
must be a logical zero while OE# is a logical one.  
Command Sequences  
Commands that may alter array data require a  
sequence of cycles as described in Table 6. This  
provides data protection against inadvertent writes.  
Power-Up Write Inhibit  
If WE# = CE# = VIL and OE# = VIH during power  
up, the device does not accept commands on the  
rising edge of WE#. The internal state machine is  
automatically reset to the Read mode on power-  
up.  
Low VCC Write Inhibit  
To protect data during VCC power-up and power-  
down, the device does not accept write cycles  
when VCC is less than VLKO (typically 2.4 volts). The  
command register and all internal program/erase  
circuits are disabled, and the device resets to the  
Read mode. Writes are ignored until VCC is greater  
than VLKO. The system must provide the proper  
signals to the control pins to prevent unintentional  
Sector Protection  
Additional data protection is provided by the  
HY29LV400s sector protect feature, described  
previously, which can be used to protect sensitive  
areas of the Flash array from accidental or unau-  
thorized attempts to alter the data.  
writes when VCC is greater than VLKO  
.
Rev. 1.0/Nov. 01  
20  
HY29LV400  
ABSOLUTE MAXIMUM RATINGS4  
Symbol  
Parameter  
Value  
Unit  
oC  
TSTG  
TBIAS  
Storage Temperature  
Ambient Temperature with Power Applied  
-65 to +150  
-65 to +125  
oC  
Voltage on Pin with Respect to VSS  
VCC 1  
:
-0.5 to +4.0  
-0.5 to +12.5  
-0.5 to VCC +0.5  
V
V
V
VIN2  
A[9], OE#, RESET# 2  
All Other Pins 1  
IOS  
Output Short Circuit Current3  
200  
mA  
Notes:  
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to  
-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage  
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10.  
2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET#  
may undershoot VSS to 2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A[9] is +12.5 V  
which may overshoot to 14.0 V for periods up to 20 ns.  
3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.  
4. Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a  
stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera-  
tional sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for  
extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS1  
Symbol  
Parameter  
Value  
Unit  
Ambient Operating Temperature:  
TA  
Commercial Temperature Devices  
Industrial Temperature Devices  
0 to +70  
-40 to +85  
oC  
oC  
Operating Supply Voltage:  
VCC  
-55 Version  
Other Versions  
+3.0 to +3.6  
+2.7 to +3.6  
V
V
Notes:  
1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.  
20 ns  
20 ns  
20 ns  
VCC + 2.0 V  
0.8 V  
- 0.5 V  
VCC + 0.5 V  
2.0 V  
- 2.0 V  
20 ns  
20 ns  
20 ns  
Figure 9. Maximum Undershoot Waveform  
Figure 10. Maximum Overshoot Waveform  
Rev. 1.0/Nov. 01  
21  
HY29LV400  
DC CHARACTERISTICS  
Parameter  
Description  
Test Setup 2  
VIN = VSS to VCC  
A[9] = 12.5 V  
VOUT = VSS to VCC  
CE# = VIL,  
Min  
Typ  
Max  
±1.0  
35  
Unit  
μA  
μA  
ILI  
ILIT  
ILO  
Input Load Current  
A[9] Input Load Current  
Output Leakage Current  
±1.0  
μA  
5 MHz  
1 MHz  
5 MHz  
1 MHz  
7
2
7
12  
4
mA  
mA  
mA  
OE# = VIH,  
Byte Mode  
CE# = VIL,  
OE# = VIH,  
ICC1  
VCC Active Read Current1  
12  
2
4
mA  
mA  
Word Mode  
ICC2  
ICC3  
VCC Active Write Current3, 4  
VCC CE# Controlled Deep  
Standby Current  
VCC RESET# Controlled Deep  
Standby Current  
Automatic Sleep Mode  
Current5,  
VCC CE# Controlled Normal  
Standby Current2  
CE# = VIL,OE# = VIH  
CE# = VCC ± 0.3 V,  
RESET# = VCC ± 0.3 V  
15  
30  
0.2  
0.2  
0.2  
5
5
5
1
1
μA  
μA  
ICC4  
ICC5  
ICC6  
ICC7  
RESET# = VSS ± 0.3 V  
VIH = VCC ± 0.3 V,  
VIL = VSS ± 0.3 V  
μA  
CE# = RESET# = VIH  
RESET# = VIL  
mA  
mA  
VCC RESET# Controlled  
Normal Standby Current2  
Input Low Voltage  
VIL  
VIH  
-0.5  
0.7 x VCC  
0.8  
VCC + 0.3  
V
V
Input High Voltage  
Voltage for Electronic ID and  
Temporary Sector Unprotect  
VID  
VOL  
VCC = 3.3V  
11.5  
12.5  
0.45  
V
V
V
VCC = VCC Min,  
IOL = 4.0 mA  
VCC = VCC Min,  
IOH = -2.0 mA  
VCC = VCC Min,  
Output Low Voltage  
VOH1  
VOH2  
0.85 x VCC  
Output High Voltage  
VCC - 0.4  
2.3  
V
V
IOH = -100 μA  
VLKO  
Low VCC Lockout Voltage4  
2.5  
Notes:  
1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. Typical VCC is 3.0 V.  
2. All specifications are tested with VCC = VCC Max unless otherwise noted.  
3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress.  
4. Not 100% tested.  
5. Automatic sleep mode is enabled when addresses remain stable for tACC + 30 ns (typical).  
Rev. 1.0/Nov. 01  
22  
HY29LV400  
DC CHARACTERISTICS  
Zero Power Flash  
20  
15  
10  
5
0
0
500  
1000  
1500  
2000  
2500  
3000  
3500  
4000  
Time in ns  
Note: Addresses are switching at 1 MHz.  
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)  
8
3.6 V  
6
2.7 V  
4
2
0
1
2
3
4
5
Frequency in MHz  
Note: T = 25 °C.  
Figure 12. Typical ICC1 Current vs. Frequency  
Rev. 1.0/Nov. 01  
23  
HY29LV400  
KEY TO SWITCHING WAVEFORMS  
WAVEFORM  
INPUTS  
OUTPUTS  
Steady  
Changing from H to L  
Changing from L to H  
Don't Care, Any Change Permitted  
Does Not Apply  
Changing, State Unknown  
Centerline is High Impedance State  
(High Z)  
TEST CONDITIONS  
Table 12. Test Specifications  
+ 3.3V  
Test  
Condition  
Output Load  
- 70  
- 90  
- 55  
Unit  
1 TTL Gate  
2.7  
KOhm  
Output Load Capacitance (CL)  
Input Rise and Fall Times  
Input Signal Low Level  
30  
100  
5
pF  
ns  
V
DEVICE  
UNDER  
TEST  
0.0  
All diodes  
Input Signal High Level  
3.0  
V
are  
1N3064  
or  
equivalent  
6.2  
KOhm  
Low Timing Measurement  
Signal Level  
CL  
1.5  
1.5  
V
V
High Timing Measurement  
Signal Level  
Note: Timing measurements are made at the reference lev-  
els specified above regardless of where the illustrations in  
the timing diagrams appear to indicate the measurement is  
made  
Figure 13. Test Setup  
3.0 V  
0.0 V  
I
nput  
1.5 V  
Measurement Level  
1.5 V  
Output  
Figure 14. Input Waveforms and Measurement Levels  
Rev. 1.0/Nov. 01  
24  
HY29LV400  
AC CHARACTERISTICS  
Read Operations  
Parameter  
Speed Option  
Description  
Test Setup  
Unit  
JEDEC Std  
- 55  
-70  
- 90  
tAVAV  
tRC Read Cycle Time 1  
Min  
55  
70  
90  
ns  
ns  
CE# = VIL  
OE# = VIL  
tAVQV  
tACC Address to Output Delay  
Max  
55  
70  
90  
tELQV  
tEHQZ  
tGLQV  
tGHQZ  
tCE Chip Enable to Output Delay  
tDF Chip Enable to Output High Z1  
tOE Output Enable to Output Delay  
tDF Output Enable to Output High Z1  
OE# = VIL  
Max  
Max  
Max  
Max  
Min  
55  
25  
30  
25  
70  
25  
30  
25  
0
90  
30  
35  
30  
ns  
ns  
ns  
ns  
ns  
CE# = VIL  
Read  
Output Enable  
tOEH  
Toggle and  
Data# Polling  
Hold Time 1  
Min  
Min  
10  
0
ns  
ns  
Output Hold Time from Addresses, CE#  
or OE#, Whichever Occurs First 1  
tAXQX  
tOH  
Notes:  
1. Not 100% tested.  
tRC  
Addresses  
CE#  
Addresses Stable  
tACC  
tOE  
OE#  
tOEH  
tDF  
WE#  
tCE  
tOH  
Outputs  
RESET#  
Output Valid  
RY/BY#  
0 V  
Figure 15. Read Operation Timings  
Rev. 1.0/Nov. 01  
25  
HY29LV400  
AC CHARACTERISTICS  
Hardware Reset (RESET#)  
Parameter  
Speed Option  
Description  
Test Setup  
Unit  
JEDEC Std  
- 55  
- 70  
- 90  
RESET# Pin Low (During Automatic  
Algorithms) to Read or Write 1  
tREADY  
Max  
Max  
20  
μs  
ns  
RESET# Pin Low (NOT During  
tREADY  
500  
Automatic Algorithms) to Read or Write 1  
tRP RESET# Pulse Width  
Min  
Min  
Max  
Min  
500  
50  
20  
0
ns  
ns  
μs  
ns  
tRH RESET# High Time Before Read 1  
tRPD RESET# Low to Standby Mode  
tRB RY/BY# Recovery Time  
Notes:  
1. Not 100% tested.  
RY/BY#  
0 V  
CE#, OE#  
RESET#  
tRH  
tRP  
tReady  
Reset Timings NOT During Automatic Algorithms  
tReady  
RY/BY#  
CE#, OE#  
RESET#  
tRB  
tRP  
Reset Timings During Automatic Algorithms  
Figure 16. RESET# Timings  
Rev. 1.0/Nov. 01  
26  
HY29LV400  
AC CHARACTERISTICS  
Word/Byte Configuration (BYTE#)  
Parameter  
Speed Option  
Description  
Unit  
JEDEC Std  
- 55  
- 70  
5
- 90  
tELFL CE# to BYTE# Switching Low  
Max  
Max  
Max  
Min  
ns  
ns  
ns  
ns  
tELFH CE# to BYTE# Switching High  
5
tFLQZ BYTE# Switching Low to Output High-Z  
tFHQV BYTE# Switching High to Output Active  
25  
55  
25  
70  
30  
90  
CE#  
OE#  
BYTE#  
BYTE#  
tELFL  
switching  
from word to  
byte mode  
Data Output DQ[14:0]  
Data Output DQ[7:0]  
Address Input A-1  
DQ[14:0]  
Output DQ[15]  
DQ[15]/A-1  
tFLQZ  
BYTE#  
BYTE#  
switching  
Data Output DQ[7:0]  
Data Output DQ[14:0]  
Data Output DQ[15]  
DQ[14:0]  
from byte to  
word mode  
Address Input A-1  
DQ[15]/A-1  
tELFH  
tFHQV  
Figure 17. BYTE# Timings for Read Operations  
CE#  
Falling edge of the last WE# signal  
WE#  
tSET (tAS  
)
BYTE#  
tHOLD (tAH  
)
Note: Refer to the Program/Erase Operations table for tAS and tAH specifications.  
Figure 18. BYTE# Timings for Write Operations  
Rev. 1.0/Nov. 01  
27  
HY29LV400  
AC CHARACTERISTICS  
Program and Erase Operations  
Parameter  
Speed Option  
Description  
Unit  
JEDEC Std  
- 55  
- 70  
70  
0
- 90  
tAVAV  
tAVWL  
tWLAX  
tDVWH  
tWHDX  
tGHWL  
tELWL  
tWHEH  
tWLWH  
tWHWL  
tWC Write Cycle Time 1  
tAS Address Setup Time  
tAH Address Hold Time  
tDS Data Setup Time  
tDH Data Hold Time  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Typ  
55  
90  
ns  
ns  
35  
35  
45  
35  
0
45  
45  
ns  
ns  
ns  
tGHWL Read Recovery Time Before Write  
tCS CE# Setup Time  
0
ns  
0
ns  
tCH CE# Hold Time  
0
ns  
tWP Write Pulse Width  
35  
35  
30  
9
35  
ns  
tWPH Write Pulse Width High  
ns  
μs  
Byte Mode  
Word Mode  
Byte Mode  
Word Mode  
Max  
Typ  
300  
11  
360  
4.5  
13.5  
2.9  
8.7  
0.5  
10  
μs  
tWHWH1 tWHWH1 Programming Operation 1, 2, 3  
μs  
Max  
Typ  
μs  
sec  
sec  
sec  
sec  
sec  
sec  
Max  
Typ  
Chip Programming Operation 1, 2, 3, 5  
Max  
Typ  
tWHWH2 tWHWH2 Sector Erase Operation 1, 2, 4  
tWHWH3 tWHWH3 Chip Erase Operation 1, 2, 4  
Erase and Program Cycle Endurance 1  
Max  
Typ  
5
sec  
Typ  
Min  
Min  
Min  
Min  
1,000,000  
cycles  
cycles  
μs  
100,000  
tVCS VCC Setup Time 1  
50  
0
tRB Recovery Time from RY/BY#  
tBUSY WE# High to RY/BY# Delay  
ns  
90  
ns  
Notes:  
1. Not 100% tested.  
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 3.0 volts, 100,000 cycles. In addition,  
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-  
tions of 90 °C, VCC = 2.7 volts (3.0 volts for - 55 version), 100,000 cycles.  
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program  
command. See Table 6 for further information on command sequences.  
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are  
programmed to 0x00 before erasure.  
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most  
bytes/words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the  
maximum byte/word program time specified is exceeded. See Write Operation Status section for additional information.  
Rev. 1.0/Nov. 01  
28  
HY29LV400  
AC CHARACTERISTICS  
Program Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
tW C  
tAS  
tAH  
Addresses  
CE#  
0x555  
PA  
PA  
PA  
tG H W L  
OE#  
tCH  
tW P  
WE#  
tCS  
tW P H  
tDH  
tDS  
tW H W H 1  
Data  
0xA0  
PD  
tBUSY  
Status  
DOUT  
tRB  
RY/BY#  
VCC  
tVCS  
Notes:  
1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address.  
2. Commands shown are for Word mode operation.  
3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.  
Figure 19. Program Operation Timings  
Rev. 1.0/Nov. 01  
29  
HY29LV400  
AC CHARACTERISTICS  
Erase Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
tW C  
tAS  
tAH  
Addresses  
CE#  
0x2AA  
SA  
VA  
VA  
Address = 0x555  
for chip erase  
tG H W L  
OE#  
tCH  
tW P  
WE#  
tW H W H 2 or  
tW H W H 3  
tCS  
tW P H  
tDS  
Data = 0x10  
for chip erase  
tDH  
Data  
0x55  
0x30  
tBUSY  
Status  
DOUT  
tRB  
RY/BY#  
VCC  
tVCS  
Notes:  
1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),  
OUT is the true data at the read address.(0xFF after an erase operation).  
D
2. Commands shown are for Word mode operation.  
3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.  
Figure 20. Sector/Chip Erase Operation Timings  
Rev. 1.0/Nov. 01  
30  
HY29LV400  
AC CHARACTERISTICS  
tRC  
VA  
Addresses  
VA  
VA  
tACC  
tCH  
CE#  
tCE  
OE#  
tDF  
tOEH  
WE#  
tOE  
tOH  
Complement  
Status Data  
Complement  
True  
Valid Data  
DQ[7]  
DQ[6:0]  
RY/BY#  
Status Data  
Data  
Valid Data  
tBUSY  
Notes:  
1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).  
2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.  
Figure 21. Data# Polling Timings (During Automatic Algorithms)  
tRC  
Addresses  
CE#  
VA  
VA  
VA  
VA  
tACC  
tCH  
tCE  
OE#  
tDF  
tOEH  
WE#  
tOE  
tOH  
Valid Status  
(first read)  
Valid Status  
(second read)  
Valid Status  
Valid Data  
DQ[6], [2]  
(stops toggling)  
tBUSY  
RY/BY#  
Notes:  
1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section).  
2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.  
Figure 22. Toggle Polling Timings (During Automatic Algorithms)  
Rev. 1.0/Nov. 01  
31  
HY29LV400  
AC CHARACTERISTICS  
Enter Erase  
Suspend  
Program  
Enter Automatic  
Erase  
Erase  
Suspend  
Erase  
Resume  
WE#  
Erase  
Erase  
Erase  
Erase  
Erase  
Erase  
Suspend  
Read  
Suspend  
Program  
Suspend  
Read  
Complete  
DQ[6]  
DQ[2]  
Notes:  
1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an  
erase-suspended sector.  
Figure 23. DQ[2] and DQ[6] Operation  
Sector Protect and Unprotect, Temporary Sector Unprotect  
Parameter  
Speed Option  
Description  
Unit  
JEDEC Std  
- 55  
- 70  
- 90  
tVIDR VID Transition Time for Temporary Sector Unprotect1  
Min  
Min  
500  
ns  
μs  
RESET# Setup Time for  
tRSP  
4
1
Temporary Sector Unprotect  
RESET# Setup Time for Sector Protect and  
Unprotect  
tVRES  
Min  
μs  
tPROT Sector Protect Time  
tUNPR Sector Unprotect Time  
Max  
Max  
150  
15  
μs  
ms  
Notes:  
1. Not 100% tested.  
VID  
RESET#  
0 or 3V  
0 or 3V  
tVIDR  
tVIDR  
CE#  
WE#  
tRSP  
RY/BY#  
Figure 24. Temporary Sector Unprotect Timings  
Rev. 1.0/Nov. 01  
32  
HY29LV400  
AC CHARACTERISTICS  
VID  
VIH  
RESET#  
SA, A[6],  
A[1], A[0]  
Don't Care  
Valid *  
Valid *  
Verify  
0x40  
Valid *  
Sector Protect/Unprotect  
0x60  
0x60  
Status  
Data  
tVRES  
tPROT  
CE#  
WE#  
OE#  
tU N P R  
Note: For Sector Protect, A[6] = 0, A[1] = 1, A[0] = 0. For Sector Unprotect, A[6] = 1, A[1] = 1, A[0] = 0.  
Figure 25. Sector Protect and Unprotect Timings  
Alternate CE# Controlled Program and Erase Operations2  
Parameter  
Speed Option  
Description  
Unit  
JEDEC Std  
- 55  
- 70  
70  
0
- 90  
tAVAV  
tAVEL  
tELAX  
tDVEH  
tEHDX  
tGHEL  
tWLEL  
tEHWH  
tELEH  
tEHEL  
tWC Write Cycle Time 1  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
55  
90  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAS Address Setup Time  
tAH Address Hold Time  
tDS Data Setup Time  
tDH Data Hold Time  
45  
35  
45  
35  
0
45  
45  
tGHEL Read Recovery Time Before Write  
tWS WE# Setup Time  
0
0
tWH WE# Hold Time  
0
tCP CE# Pulse Width  
35  
35  
30  
90  
35  
tCPH CE# Pulse Width High  
tBUSY CE# to RY/BY# Delay  
Notes:  
1. Not 100% tested.  
2. See Program and Erase Operations table for program and erase characteristics.  
Rev. 1.0/Nov. 01  
33  
HY29LV400  
AC CHARACTERISTICS  
PA for Program  
SA for Sector Erase  
0x555 for Chip Erase  
0x555 for Program  
0x2AA for Erase  
Addresses  
VA  
tW C  
tAS  
tAH  
WE#  
OE#  
CE#  
tGHEL  
tW H  
tCP  
tCPH  
tW H W H 1 or tW H W H 2 or tW H W H 3  
tW S  
tDS  
tDH  
tBUSY  
Data  
Status  
D OUT  
0xA0 for Program  
0x55 for Erase  
PD for Program  
0x30 for Sector Erase  
0x10 for Chip Erase  
RY/BY#  
tRH  
RESET#  
Notes:  
1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write Opera-  
tion Status section), DOUT = array data read at VA.  
2. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.  
3. Word mode addressing shown.  
4. RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command  
sequence.  
Figure 26. Alternate CE# Controlled Write Operation Timings  
Rev. 1.0/Nov. 01  
34  
HY29LV400  
Latchup Characteristics  
Description  
Minimum  
Maximum  
Unit  
Input voltage with respect to VSS on all pins except I/O  
pins(including A[9], OE# and RESET#)  
- 1.0  
12.5  
V
Input voltage with respect to VSS on all I/O pins  
- 1.0  
VCC + 1.0  
100  
V
VCC Current  
- 100  
mA  
Notes:  
1. Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.  
TSOP and PSOP Pin Capacitance  
Symbol  
CIN  
Parameter  
Input Capacitance  
Test Setup  
VIN = 0  
Typ  
Max  
7.5  
12  
Unit  
pF  
6
COUT  
CIN2  
Output Capacitance  
VOUT = 0  
VIN = 0  
8.5  
7.5  
pF  
Control Pin Capacitance  
9
pF  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions: TA = 25 oC, f = 1.0 MHz.  
Data Retention  
Parameter  
Test Conditions  
Minimum  
Unit  
Years  
Years  
150 oC  
125 oC  
10  
20  
Minimum Pattern Data Retention Time  
Rev. 1.0/Nov. 01  
35  
HY29LV400  
PACKAGE DRAWINGS  
Physical Dimensions  
TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)  
0.95  
1.05  
Pin 1 ID  
1
48  
0.50 BSC  
11.90  
12.10  
24  
25  
18.30  
18.50  
0.05  
0.15  
19.80  
20.20  
0.08  
0.20  
1.20  
MAX  
0.10  
0.21  
0o  
5o  
0.25MM (0.0098") BSC  
0.50  
0.70  
Rev. 1.0/Nov. 01  
36  
HY29LV400  
PACKAGE DRAWINGS  
Physical Dimensions  
FBGA48 - 48-Ball Fine-Pitch Ball Grid Array, 6 x 8 mm (measurements in millimeters)  
Note: Unless otherwise specified, tolerance = ± 0.05  
0.10  
C
8.00 ± 0.10  
A
1.80  
± 0.10  
A1 CORNER  
INDEX AREA  
2.10 ± 0.10  
6.00 ± 0.10  
C
0.10  
C
B
C
0.10  
C
0.76  
T Y P  
1.10  
MAX  
Seating  
Plane  
0.20  
MIN  
C
0.08  
C
5.60 BSC  
H
G
F
E
D
C
B
A
6
5
4
3
2
1
0.40  
B S C  
4.00 BSC  
C
0.80 TYP  
Pin A1  
Index Mark  
0.40  
B S C  
?
0.30 ± 0.05  
? 0.15  
? 0.08  
M
M
C
C
A B  
C
Rev. 1.0/Nov. 01  
37  
HY29LV400  
ORDERING INFORMATION  
Hynix products are available in several speeds, packages and operating temperature ranges. The  
ordering part number is formed by combining a number of fields, as indicated below. Refer to the Valid  
Combinationstable, which lists the configurations that are planned to be supported in volume. Please  
contact your local Hynix representative or distributor to confirm current availability of specific configura-  
tions and to determine if additional configurations have been released.  
HY29LV400  
X
X
-
X
X
X
SPECIAL INSTRUCTIONS  
TEMPERATURE RANGE  
Blank = Commercial ( 0 to +70 °C)  
I = Industrial (-40 to +85 °C)  
SPEED OPTION  
55 = 55 ns  
70 = 70 ns  
90 = 90 ns  
PACKAGE TYPE  
T = 48-Pin Thin Small Outline Package (TSOP)  
F = 48-Ball Fine-Pitch Ball Grid Array (FBGA), 8 x 9 mm  
BOOT BLOCK LOCATION  
T = Top Boot Block Option  
B = Bottom Boot Block Option  
DEVICE NUMBER  
HY29LV400 = 4 Megabit (512K x 8/256K x 16) CMOS 3 Volt-Only  
Sector Erase Flash Memory  
VALID COMBINATIONS  
Package and Speed  
TSOP  
FBGA  
70 ns  
F-70  
Temperature  
Commercial  
Industrial  
55 ns  
T-55  
70 ns  
T-70  
90 ns  
T-90  
55 ns  
F-55  
90 ns  
F-90  
T-55I  
T-70I  
T-90I  
F-55I  
F-70I  
F-90I  
Note:  
1. The complete part number is formed by appending the suffix shown in the table above to the Device Number. For  
example, the part number for a 90 ns, top boot block, Industrial temperature range device in the TSOP package is  
HY29LV400TT-90I.  
Rev. 1.0/Nov. 01  
38  
HY29LV400  
Rev. 1.0/Nov. 01  
39  
HY29LV400  
Important Notice  
? 2001 by Hynix Semiconductor America. All rights reserved.  
No part of this document may be copied or reproduced in any  
form or by any means without the prior written consent of Hynix  
Semiconductor Inc. or Hynix Semiconductor America (collec-  
tively Hynix).  
tions of Sale only. Hynix makes no warranty, express, statu-  
tory, implied or by description, regarding the information set  
forth herein or regarding the freedom of the described devices  
from intellectual property infringement. Hynix makes no war-  
ranty of merchantability or fitness for any purpose.  
The information in this document is subject to change without  
notice. Hynix shall not be responsible for any errors that may  
appear in this document and makes no commitment to update  
or keep current the information contained in this document.  
Hynix advises its customers to obtain the latest version of the  
device specification to verify, before placing orders, that the  
information being relied upon by the customer is current.  
Hynixs products are not authorized for use as critical compo-  
nents in life support devices or systems unless a specific writ-  
ten agreement pertaining to such intended use is executed  
between the customer and Hynix prior to use. Life support  
devices or systems are those which are intended for surgical  
implantation into the body, or which sustain life whose failure to  
perform, when properly used in accordance with instructions  
for use provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
Devices sold by Hynix are covered by warranty and patent in-  
demnification provisions appearing in Hynix Terms and Condi-  
Revision Record  
Rev. Date  
Details  
1.0  
10/01 Initial release.  
Flash Memory Business Unit, Korea  
Hynix Semiconductor Inc.  
891, Daechi-dong  
Kangnam-gu  
Seoul, Korea  
Flash Memory Business Unit, HQ  
Hynix Semiconductor Inc.  
3101 North First Street  
San Jose, CA 95134  
USA  
Telephone: +82-2-3459-5980  
Fax: +82-2-3459-5988  
Telephone: (408) 232-8800  
Fax: (408) 232-8805  
http://www.hynix.com  
http://www.us.hynix.com  
Rev. 1.0/Nov. 01  
40  
配單直通車
HY29LV400TT-55產(chǎn)品參數(shù)
型號(hào):HY29LV400TT-55
生命周期:Obsolete
零件包裝代碼:TSOP
包裝說(shuō)明:TSOP1, TSSOP48,.8,20
針數(shù):48
Reach Compliance Code:compliant
ECCN代碼:EAR99
HTS代碼:8542.32.00.51
風(fēng)險(xiǎn)等級(jí):5.65
最長(zhǎng)訪問(wèn)時(shí)間:55 ns
備用內(nèi)存寬度:8
啟動(dòng)塊:TOP
命令用戶界面:YES
數(shù)據(jù)輪詢:YES
耐久性:100000 Write/Erase Cycles
JESD-30 代碼:R-PDSO-G48
JESD-609代碼:e6
長(zhǎng)度:18.4 mm
內(nèi)存密度:4194304 bit
內(nèi)存集成電路類型:FLASH
內(nèi)存寬度:16
功能數(shù)量:1
部門(mén)數(shù)/規(guī)模:1,2,1,7
端子數(shù)量:48
字?jǐn)?shù):262144 words
字?jǐn)?shù)代碼:256000
工作模式:ASYNCHRONOUS
最高工作溫度:70 °C
最低工作溫度:
組織:256KX16
封裝主體材料:PLASTIC/EPOXY
封裝代碼:TSOP1
封裝等效代碼:TSSOP48,.8,20
封裝形狀:RECTANGULAR
封裝形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL
電源:3.3 V
編程電壓:3 V
認(rèn)證狀態(tài):Not Qualified
就緒/忙碌:YES
座面最大高度:1.2 mm
部門(mén)規(guī)模:16K,8K,32K,64K
最大待機(jī)電流:0.000005 A
子類別:Flash Memories
最大壓擺率:0.03 mA
最大供電電壓 (Vsup):3.6 V
最小供電電壓 (Vsup):3 V
標(biāo)稱供電電壓 (Vsup):3.3 V
表面貼裝:YES
技術(shù):CMOS
溫度等級(jí):COMMERCIAL
端子面層:TIN BISMUTH
端子形式:GULL WING
端子節(jié)距:0.5 mm
端子位置:DUAL
切換位:YES
類型:NOR TYPE
寬度:12 mm
Base Number Matches:1
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