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HY5117804C,HY5116804C

2Mx8, Extended Data Out mode

DESCRIPTION

This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configuration with Extended Data Out mode CMOS

DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70

or 80ns) and refresh cycle(2K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s

advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and

high reliability.

FEATURES

? Extended data out operation

? Read-modify-write Capability

? TTL compatible inputs and outputs

? /CAS-before-/RAS, /RAS-only, Hidden and

Self refresh capability

? JEDEC standard pinout

? 28-pin Plastic SOJ (300mil)

28-pin plastic TSOP-II (300mil)

? Single power supply of 5V ± 10%

? Early write or output enable controlled write

? Max. Active power dissipation

? Fast access time and cycle time

Speed

60

2K refresh

660mW

4K refresh

550mW

Speed

60

tRAC

60ns

70ns

80ns

tCAC

15ns

20ns

tHPC

25ns

30ns

35ns

70

550mW

495mW

70

80

495mW

440mW

80

? Refresh cycle

Part number

HY5117804C

HY5116804C

Refresh

2K

Normal

SL-part

32ms

64ms

256ms

4K

ORDERING INFORMATION

Part Name

HY5117804CJ

Refresh

Power

SL-part

Package

28Pin SOJ

2K

4K

HY5117804CSLJ

HY5117804CT

HY5117804CSLT

HY5116804CJ

28Pin SOJ

28Pin TSOP-II

28Pin SOJ

HY5116804CSLJ

HY5116804CT

HY5116804CSLT

28Pin SOJ

28Pin TSOP-II

*SL : Low power with self refresh

This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of

circuits described. No patent licences are implied

Hyundai Semiconductor

Rev.00 / Sep.97

1

HY5117804C,HY5116804C

FUNCTIONAL BLOCK DIAGRAM

2Mx8,EDO DRAM

Rev.00 / Sep.97

2

HY5117804C,HY5116804C

PIN CONFIGURATION (Marking Side)

28Pin Plastic SOJ (300mil)

28Pin Plastic TSOP- II (300mil)

*(N.C) : For 2K Refresh product

PIN DESCRIPTION

Pin Name

/RAS

Parameter

Row Address Strobe

/CAS

/WE

Column Address Strobe

Write Enable

/OE

Output Enable

A0~A11

A0~A10

DQ0~DQ7

Vcc

Address Input (4K Refresh Product)

Address Input (2K Refresh Product)

Data In/Out

Power (5V)

Vss

Ground

NC

No Connection

2Mx8,EDO DRAM

Rev.00 / Sep.97

3

HY5117804C,HY5116804C

ABSOLUTE MAXIMUM RATING

Symbol

Parameter

Rating

0 to 70

-55 to 150

-1.0 to 7.0

50

Unit

TA

Ambient Temperature

°C

TSTG

Storage Temperature

°C

VIN, VOUT

VCC

Voltage on Any Pin relative to VSS

Voltage on VCC relative to VSS

Short Circuit Output Current

Power Dissipation

V

IOS

mA

PD

1

W

TSOLDER

Soldering Temperature ? Time

260 ? 10

°C ? sec

Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0°C to 70°C )

Symbol

VCC

Parameter

Min

4.5

Typ

Max

5.5

UNIT

Power Supply Voltage

Input High Voltage

Input Low Voltage

5.0

V

VIH

2.4

-

VCC+1.0

0.8

VIL

-1.0

Note : All voltages are referenced to VSS.

DC OPERATING CHARACTERISTIC

Symbol

Parameter

Test condition

Min

Max

Unit

ILI

Input Leakage Current

(Any input)

VSS ￡ VIN ￡ VCC + 1.0

All other pins not under test = VSS

-10

10

0.4

-

mA

V

ILO

Output Leakage Current

(Any input)

VSS ￡ VOUT ￡ VCC

/RAS & /CAS at VIH

-10

-

VOL

VOH

Output Low Voltage

Output High Voltage

IOL = 4.2mA

IOH = -5.0mA

2.4

V

2Mx8,EDO DRAM

Rev.00 / Sep.97

4

HY5117804C,HY5116804C

DC CHARACTERISTICS

(TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.)

Max. Current

Symbol

Parameter

Test condition

Speed

Unit

2K Ref

4K Ref

60

70

80

120

100

90

100

90

80

ICC1

ICC2

ICC3

Operating Current

/RAS, /CAS Cycling

tRC = tRC(min.)

mA

TTL Standby

Current

/RAS, /CAS 3 VIH

Other inputs 3 VSS

2

1

2

1

SL-part

60

70

80

120

100

90

100

90

80

/RAS-only Refresh

Current

/RAS Cycling,/CAS = VIH

tRC = tRC(min.)

60

70

80

100

90

80

90

80

70

ICC4

ICC5

ICC6

EDO mode Current

/CAS Cycling, /RAS = VIL

tHPC = tHPC(min.)

mA

CMOS Standby

Current

1

200

1

200

mA

/RAS = /CAS 3 VCC - 0.2V

SL-part

60

70

80

120

100

90

100

90

80

/CAS-before-/RAS

Refresh Current

/RAS & /CAS = 0.2V

tRC = tRC(min.)

mA

tRAS ￡

300ns

ICC7

ICC8

Battery Back-up

Current (SL-part)

tRC=250μs (2K Ref), 62.5μs (4K Ref)

/CAS = 0.2V

/OE & /WE = VCC - 0.2V

Address = Vcc-0.2V or 0.2V

DQ0~DQ7 = Vcc-0.2, 0.2V or Open

300

mA

tRAS ￡

1μs

400

300

400

300

Self Refresh Current

(SL-part)

/RAS & /CAS = 0.2V

Other pins are same as ICC7

Note

1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tHPC).

2. Specified values are obtained with output unloaded.

3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,

address can be changed maximum once while /CAS=VIH within one EDO mode cycle time tHPC.

4. Only /RAS(max.) = 1μs is applied to refresh of battery backup but tRAS(max.) = 10μs is to applied to normal functional

operation.

5. Icc5(max.) = 200μA, Icc7 and Icc8 are applied to SL-part only.

2Mx8,EDO DRAM

Rev.00 / Sep.97

5

HY5117804C,HY5116804C

AC CHARACTERISTICS

(TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.)

60ns

70ns

80ns

Symbol

Unit

Note

Parameter

Min

105

142

25

73

-

Max

Min

Max

Min

Max

tRC

-

125

167

30

85

-

ns

Random read or write cycle time

Read-modify-write cycle time

EDO mode cycle time

145

187

35

100

-

tRWC

tHPC

tHPRWC

tRAC

tCAC

tAA

-

2

-

EDO mode read-modify-write cycle time

Access time from /RAS

-

60

70

5,6,7

5,6

5

80

-

15

-

20

Access time from /CAS

-

20

-

30

-

35

Access time from column address

Access time from /CAS precharge

/CAS to output low impedance

Output buffer turn-off delay from /CAS

Transition time(rise and fall)

/RAS precharge time

-

40

tCPA

tCLZ

tCEZ

tT

-

35

-

35

5

-

40

0

-

0

-

5

0

-

3

15

3

15

8,12

3

15

3

50

3

50

3

50

tRP

40

60

13

45

13

20

15

5

-

50

70

15

50

15

20

15

5

-

60

80

20

60

20

15

5

-

tRAS

tRASP

tRSH

tCSH

tCAS

tRCD

tRAD

tCRP

tCP

10K

/RAS pulse width

10K

100K

/RAS pulse width(EDO mode)

/RAS hold time

100K

-

/CAS hold time

-

10K

/CAS pulse width

10K

45

30

-

50

35

-

6

7

/RAS to /CAS delay time

60

40

-

/RAS to column address delay time

/CAS to /RAS precharge time

/CAS precharge time

7

-

10

0

-

10

0

-

tASR

tRAH

tASC

tCAH

tRAL

tRCS

tRCH

tRRH

tWCH

tWP

0

-

Row address set-up time

-

10

0

-

10

0

-

Row address hold time

10

0

-

Column address set-up time

Column address hold time

Column address to /RAS lead time

Read command set-up time

Read command hold time referenced to /CAS

Read command hold time referenced to /RAS

Write command hold time

-

10

30

0

-

15

35

0

-

15

40

0

-

0

-

0

-

9

0

-

0

-

0

-

0

-

10

15

13

-

15

10

15

-

15

10

15

20

-

Write command pulse width

Write command to /RAS lead time

Write command to /CAS lead time

-

tRWL

tCWL

-

16

-

2Mx8,EDO DRAM

Rev.00 / Sep.97

6

HY5117804C,HY5116804C

AC CHARACTERISTICS

Continued

60ns

70ns

80ns

Symbol

Parameter

Unit

Note

Min

Max

Min

Max

Min

Max

tDS

tDH

Data-in set-up time

0

10

-

0

15

-

ns

ms

ns

10

0

15

-

Data-in hold time

-

Refresh period(2048 cycles)

Refresh period(4096 cycles)

Refresh period(SL-part)

32

tREF

-

64

-

64

-

64

-

256

-

256

-

256

tWCS

tCWD

tRWD

tAWD

tCSR

tCHR

tRPC

tCPT

Write command set-up time

/CAS to /WE delay time

0

-

0

-

11

11,15

11

0

-

37

80

50

5

45

95

60

5

45

105

65

5

/RAS to /WE delay time

-

Column address to /WE delay time

/CAS set-up time(CBR cycle)

/CAS hold time(CBR cycle)

/RAS to /CAS precharge time

/CAS precharge time(CBR counter test)

/RAS hold time referenced to /OE

/OE access time

-

11

-

17

-

10

5

-

10

5

-

18

10

5

-

30

10

-

35

10

-

14

40

10

-

tROH

tOEA

tOED

tOEZ

tOEH

tCPWD

tRHCP

tWRP

tWRH

tRASS

tRPS

tCHS

tDOH

tREZ

-

15

-

20

-

20

-

/OE to data delay time

15

3

20

3

20

3

Output buffer turn-off delay time from /OE

/OE command hold time

15

-

15

-

8

15

-

15

55

40

10

100K

110

-50

5

20

65

40

10

100K

130

-50

5

20

75

50

10

100K

150

-50

5

/WE delay time from /CAS precharge

/RAS hold time from /CAS precharge

/WE to /RAS precharge time(CBR cycle)

/WE to /RAS hold time(CBR cycle)

/RAS pulse width(self refresh)

/RAS Precharge Time (Self refresh)

/CAS Hold Time (Self refresh)

Output Data Hold Time

-

11

-

Output Buffer Turn Off Delay Time from /RAS

Output Buffer Turn Off Delay Time from /WE

/WE to Data Delay Time

3

15

-

3

15

-

3

15

-

tWEZ

tWED

tOEP

tWPE

tOCH

tCHO

3

15

5

15

5

15

5

/OE Precharge Time

-

/WE Pulse Width (EDO cycle)

/OE to /CAS Hold Time

5

-

5

-

5

-

5

-

5

-

5

-

/CAS Hold Time to /OE

5

-

5

-

5

-

2Mx8,EDO DRAM

Rev.00 / Sep.97

7

HY5117804C,HY5116804C

NOTE

1. An initial pause of 200ms is required after power-up followed by 8 /RAS only refresh cycles before proper

device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of

8 /RAS-only refresh cycles are required.

2 tASC 3 tCP(min), assume tT=3ns.

3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured

between VIH(min.) and VIL(max.)

4. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature

range (TA=0 to 70? C?) is assured.

5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF.

6. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.

7. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.

If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.

8. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced

to output voltage levels.

9. Either tRCH or tRRH must be satisfied for a read cycle.

10.These parameters are referenced to /LCAS or /UCAS leading edge in early write cycles and to /WE leading edge in

read-modify-write cycles and late write cycle.

11.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If tWCS 3 tWCS(min.), the cycle is an early write cycle and data out pin will remain open

circuit (high impedance) through the entire cycle. If tRWD 3 tRWD(min.), tCWD 3 tCWD(min.), tAWD 3 tAWD(min), and tCPWD 3

tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither

of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.

12.If /RAS goes to high before /CAS high going,the open circuit condition of the output is achieved by /CAS high going. If

/CAS goes to high before /RAS high going,the open circuit condition of the output is achieved by /RAS high going.

13.tASC,tCAH are referenced to the earlier /CAS falling edge.

14.tCP and tCPT are measured when /CAS is high state.

15.tCWD is referenced to the later /CAS falling edge at word read-modifiy-write cycle.

16.tCWL must be satisfied by /CAS for 8-bit access cycles.

17.tCSR is referenced to the earlier /CAS falling before /RAS transition low.

18.tCHR is referenced to the later /CAS rising high after /RAS transition low.

CAPACITANCE

(TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.)

Symbol

Parameter

Input Capacitance (A0~A11)

Typ.

Max

Unit

pF

CIN1

-

5

7

CIN2

CDQ

Input Capacitance (/RAS, /CAS, /WE, /OE)

Data Input / Output Capacitance (DQ0~DQ7)

pF

2Mx8,EDO DRAM

Rev.00 / Sep.97

8

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