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產(chǎn)品型號(hào)HY27UF081G2A-TPIB的Datasheet PDF文件預(yù)覽

HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
1Gb NAND FLASH  
HY27UF081G2A  
HY27UF161G2A  
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for  
use of circuits described. No patent licenses are implied.  
Rev 0.4 / Jun. 2007  
1
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Document Title  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory  
Revision History  
Revision  
History  
No.  
Draft Date  
Remark  
0.01  
Dec. 28. 2005 Preliminary  
Initial Draft.  
1) Change NOP  
2) Change AC Characteristics  
tOH  
0.1  
May. 18. 2006 Preliminary  
Before  
After  
12  
10  
1) Delete Memory array map  
2) Change AC Characteristics  
tCS  
tCEA  
35  
tREA  
25  
0.2  
Oct. 02. 2006 Preliminary  
Before  
After  
25  
20  
25  
20  
3) Correct copy back function  
1) Change 1Gb Package Type  
- FBGA package is added  
0.3  
0.4  
Nov. 23. 2006  
Jun. 11. 2007  
- Figure & dimension are changed  
2) Delet Preliminary  
1) Correct figure 19  
Rev 0.4 / Jun. 2007  
2
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
FEATURES SUMMARY  
HIGH DENSITY NAND FLASH MEMORIES  
FAST BLOCK ERASE  
- Block erase time: 2ms (Typ.)  
- Cost effective solutions for mass storage applications  
STATUS REGISTER  
NAND INTERFACE  
- x8 or x16 bus width.  
- Multiplexed Address/ Data  
- Pinout compatibility for all densities  
ELECTRONIC SIGNATURE  
- 1st cycle: Manufacturer Code  
- 2nd cycle: Device Code  
- 3rd cycle: Internal chip number, Cell Type, Number of  
Simultaneously Programmed Pages.  
SUPPLY VOLTAGE  
- VCC = 2.7 to 3.6V : HY27UFxx1G2A  
- 4th cycle: Page size, Block size, Organization, Spare  
size  
Memory Cell Array  
= (2K+64) Bytes x 64 Pages x 1,024 Blocks  
= (1K+32) Bytes x 64 Pages x 1,024 Blocks  
SERIAL NUMBER OPTION  
CHIP ENABLE DON’T CARE  
PAGE SIZE  
- Simple interface sith microcontroller  
- x8 device : (2K+64 spare) Bytes  
: HY27UF081G2A  
DATA RETENTION  
- 100,000 Program/Erase cycles (with 1bit/528byte ECC)  
- 10 years Data Retention  
- x16 device : (1K+32 spare) Bytes  
: HY27UF161G2A  
PACKAGE  
BLOCK SIZE  
- HY27UF(08/16)1G2A-T(P)  
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)  
- HY27UF(08/16)1G2A-T (Lead)  
- HY27UF(08/16)1G2A-TP (Lead Free)  
- x8 device: (128K + 4K spare) Bytes  
- x16 device: (64K + 2K spare) Words  
PAGE READ / PROGRAM  
- Random access: 25us (max.)  
- Sequential access: 30ns (min.)  
- Page program time: 200us (typ.)  
- HY27UF081G2A-S(P)  
: 48-Pin USOP1 (12 x 17 x 0.65 mm)  
- HY27UF081G2A-S (Lead)  
- HY27UF081G2A-SP (Lead Free)  
COPY BACK PROGRAM MODE  
- Fast page copy without external buffering  
- HY27UF081G2A-F(P)  
: 63-Ball FBGA (9 x 11 x 1.0 mm)  
- HY27UF081G2A-F (Lead)  
- HY27UF081G2A-FP (Lead Free)  
CACHE PROGRAM  
- Internal (2048+64) Byte buffer to improve the program  
throughput  
Rev 0.4 / Jun. 2007  
3
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
1. SUMMARY DESCRIPTION  
The Hynix HY27UF(08/16)1G2A series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc  
Power Supply.  
Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided  
into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.  
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected  
Flash cells.  
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in  
typical 2ms on a 128K-byte(X8 device) block.  
Data in the page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data  
input/output as well as command input. This interface allows a reduced pin count and easy migration towards different  
densities, without any rearrangement of footprint.  
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Pro-  
gram/Erase Controller automates all program and erase functions including pulse repetition, where required, and inter-  
nal verification and margining of data.  
The modify operations can be locked using the WP input pin or using the extended lock block feature described later.  
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-  
ple memories the R/B pins can be connected all together to provide a global status signal.  
Even the write-intensive systems can take advantage of the HY27UF(08/16)1G2A extended reliability of 100K pro-  
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.  
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from  
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.  
The copy back function allows the optimization of defective blocks management: when a page program operation fails  
the data can be directly programmed in another page inside the same array section without the time consuming serial  
data insertion phase.  
The cache program feature allows the data insertion in the cache register while the data register is copied into the  
flash array. This pipelined program operation improves the program throughput when long files are written inside the  
memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput  
when consecutive pages have to be streamed out.  
The HYNIX HY27UF(08/16)1G2A series is available in 48 - TSOP1 12 x 20 mm, 48 - USOP 12 x 17 mmm, FBGA 9 x  
11 mm.  
1.1 Product List  
PART NUMBER  
HY27UF081G2A  
HY27UF161G2A  
ORIZATION  
VCC RANGE  
PACKAGE  
63FBGA / 48TSOP1 / 48USOP1  
48TSOP1  
x8  
2.7V - 3.6 Volt  
x16  
Rev 0.4 / Jun. 2007  
4
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
9&&  
,2?a,2?  
&(  
,2?a,2????[???RQO\?  
:(  
5?%  
5(  
$/(  
&/(  
:3  
966  
Figure1: Logic Diagram  
IO15 - IO8  
IO7 - IO0  
CLE  
Data Input / Outputs (x16 only)  
Data Inputs / Outputs  
Command latch enable  
Address latch enable  
Chip Enable  
ALE  
CE  
RE  
Read Enable  
WE  
Write Enable  
WP  
Write Protect  
R/B  
Ready / Busy  
Vcc  
Power Supply  
Vss  
Ground  
NC  
No Connection  
Table 1: Signal Names  
Rev 0.4 / Jun. 2007  
5
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
?
??  
1&  
1&  
1&  
1&  
1&  
1&  
5?%  
5(  
9VV  
?
??  
1&  
1&  
1&  
1&  
1&  
1&  
5?%  
5(  
1&  
1&  
1&  
1&  
,?2?  
,?2?  
,?2?  
,?2?  
1&  
1&  
1&  
9FF  
9VV  
1&  
1&  
1&  
,?2?  
,?2?  
,?2?  
,?2?  
1&  
1&  
1&  
1&  
,?2??  
,?2?  
,?2??  
,?2?  
,?2??  
,?2?  
,?2??  
,?2?  
1&  
1&  
9FF  
1&  
1&  
&(  
&(  
1&  
1&  
9FF  
9VV  
1&  
1&  
&/(  
$/(  
:(  
:3  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
9FF  
9VV  
1&  
1&  
&/(  
$/(  
:(  
:3  
1&  
1&  
1&  
1&  
1&  
1$1'?)ODVK  
7623?  
1$1'?)ODVK  
7623?  
??  
??  
??  
??  
??  
??  
??  
??  
1&  
?[???  
?[??  
,?2??  
,?2?  
,?2??  
,?2?  
,?2?  
,?2?  
,?2?  
,?2?  
9VV  
??  
??  
??  
??  
Figure 2. 48TSOP1 Contactions, x8 and x16 Device  
?
??  
1&  
1&  
1&  
1&  
1&  
1&  
5?%  
5(  
1&  
1&  
1&  
1&  
,?2?  
,?2?  
,?2?  
,?2?  
1&  
&(  
1&  
1&  
1&  
9FF  
9VV  
1&  
1&  
&/(  
$/(  
:(  
:3  
1&  
1&  
1&  
1&  
1&  
1&  
1$1'?)ODVK  
8623?  
9FF  
9VV  
1&  
1&  
1&  
,?2?  
,?2?  
,?2?  
,?2?  
1&  
??  
??  
??  
??  
?[??  
1&  
1&  
1&  
??  
??  
Figure 3. 48USOP1 Contactions, x8  
Rev 0.4 / Jun. 2007  
6
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
??????????????????????????????????????????????????????????????????????????  
$
%
1&  
1&  
1&  
1&  
1&  
1&  
1&  
&
$/( 9VV  
5?%  
1&  
:3  
1&  
1&  
&(  
1&  
:(  
1&  
'
&/(  
5(  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
9FF  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
9FF  
(
)
1&  
1&  
1&  
1&  
9VV  
1&  
*
+
-
,?2?  
,?2?  
,?2?  
,?2? ,?2?  
9VV  
,?2? ,?2?  
,?2?  
.
/
1&  
1&  
1&  
1&  
1&  
1&  
1&  
1&  
0
Figure 4. 63FBGA Contactions, x8 Device (Top view through package)  
Rev 0.4 / Jun. 2007  
7
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
1.2 PIN DESCRIPTION  
Pin Name  
Description  
DATA INPUTS/OUTPUTS  
The IO pins allow to input command, address and data and to output data during read / program  
IO0-IO7  
IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to  
High-Z when the device is deselected or the outputs are disabled.  
COMMAND LATCH ENABLE  
CLE  
ALE  
CE  
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of  
Write Enable (WE).  
ADDRESS LATCH ENABLE  
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of  
Write Enable (WE).  
CHIP ENABLE  
This input controls the selection of the device. When the device is busy CE low does not deselect the  
memory.  
WRITE ENABLE  
WE  
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise  
edge of WE.  
READ ENABLE  
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is  
valid tREA after the falling edge of RE which also increments the internal column address counter by  
one.  
RE  
WRITE PROTECT  
WP  
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)  
operations.  
READY BUSY  
R/B  
The Ready/Busy output is an Open Drain pin that signals the state of the memory.  
SUPPLY VOLTAGE  
The VCC supplies the power for all the operations (Read, Write, Erase).  
VCC  
VSS  
NC  
GROUND  
NO CONNECTION  
Table 2: Pin Description  
NOTE:  
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple  
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required  
during program and erase operations.  
Rev 0.4 / Jun. 2007  
8
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
IO0  
A0  
IO1  
A1  
IO2  
A2  
IO3  
A3  
IO4  
IO5  
IO6  
IO7  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
A4  
A5  
A6  
A7  
L(1)  
A16  
A24  
L(1)  
L(1)  
L(1)  
A8  
A9  
A10  
A14  
A11  
A15  
A12  
A20  
A13  
A21  
A17  
A18  
A19  
A22  
A23  
A25  
A26  
A27  
Table 3: Address Cycle Map(x8)  
NOTE:  
1. L must be set to Low.  
IO0  
IO1  
A1  
IO2  
A2  
IO3  
IO4  
IO5  
IO6  
IO7  
IO8-IO15  
L(1)  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
A0  
A8  
A3  
A4  
A5  
A6  
A7  
L(1)  
L(1)  
L(1)  
A16  
A24  
L(1)  
L(1)  
L(1)  
A9  
A10  
A13  
L(1)  
A11  
A19  
A12  
A14  
A15  
A17  
A18  
A20  
A21  
A22  
A23  
A25  
A26  
L(1)  
Table 4: Address Cycle Map(x16)  
NOTE:  
1. L must be set to Low.  
Acceptable command  
during busy  
FUNCTION  
1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE  
READ 1  
00h  
00h  
90h  
FFh  
80h  
85h  
60h  
70h  
80h  
85h  
05h  
00h  
34h  
30h  
35h  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
READ FOR COPY-BACK  
READ ID  
RESET  
-
Yes  
Yes  
PAGE PROGRAM  
COPY BACK PGM  
BLOCK ERASE  
10h  
10h  
D0h  
-
READ STATUS REGISTER  
CACHE PROGRAM  
15h  
-
RANDOM DATA INPUT  
RAMDOM DATA OUTPUT  
CACHE READ START  
CACHE READ EXIT  
E0h  
31h  
-
Table 5: Command Set  
Rev 0.4 / Jun. 2007  
9
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
CLE  
H
L
ALE  
L
CE  
L
WE  
Rising  
Rising  
Rising  
Rising  
Rising  
H
RE  
WP  
MODE  
H
X
Command Input  
Address Input(4 cycles)  
Command Input  
Address Input(4 cycles)  
Read Mode  
H
L
L
H
X
H
L
L
H
H
Write Mode  
Data Input  
H
L
L
H
H
L
L
H
H
L(1)  
L
L
L
Falling  
X
Sequential Read and Data Output  
During Read (Busy)  
During Program (Busy)  
During Erase (Busy)  
Write Protect  
L
L
H
H
X
X
X
X
X
X
X
X
X
H
X
X
X
X
H
L
X
X
X
X
X
X
H
X
0V/Vcc  
Stand By  
Table 6: Mode Selection  
NOTE:  
1. With the CE high during latency time does not stop the read operation  
Rev 0.4 / Jun. 2007  
10  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
2. BUS OPERATION  
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,  
Data Output, Write Protect, and Standby.  
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not  
affect bus operations.  
2.1 Command Input.  
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip  
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising  
edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must  
be high. See figure 6 and table 13 for details of the timings requirements. Command codes are always applied on  
IO7:0, disregarding the bus configuration (X8/X16).  
2.2 Address Input.  
Address Input bus operation allows the insertion of the memory address. To insert the 28 addresses needed to access  
the 1Gbit 4 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch Enable  
High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for  
commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 7 and table 16  
for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration  
(X8/X16).  
2.3 Data Input.  
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and  
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command  
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure  
8 and table 13 for details of the timings requirements.  
2.4 Data Output.  
Data Output bus operation allows to read data from the memory array and to check the status register content, the  
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write  
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 9,10,12,13 and table 13 for  
details of the timings requirements.  
2.5 Write Protect.  
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not  
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-  
tection even during the power up.  
2.6 Standby.  
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.  
Rev 0.4 / Jun. 2007  
11  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
3. DEVICE OPERATION  
3.1 Page Read.  
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h  
to the command register along with four address cycles. In two consecutive read operations, the second one does  
need 00h command, which four address cycles and 30h command initiates that operation. Second read operation  
always requires setup command if first read operation was executed using also random data out command.  
Two types of operations are available: random read. The random read mode is enabled when the page address is  
changed. The 2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to  
the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by  
analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in  
30ns cycle time (3.3V device) by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make  
the device output the data starting from the selected column address up to the last column address.  
The device may output random data in a page instead of the consecutive sequential data by writing random  
data output command. The column address of next data, which is going to be out, may be changed to the address  
which follows random data output command.  
Random data output can be operated multiple times regardless of how many times it is done in a page.  
Random data output is not available in cache read.  
3.2 Page Program.  
The device is programmed basically by page, but it does allow multiple partial page programming of a word or consec-  
utive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle.  
The number of consecutive partial page programming operation within the same page without an intervening erase  
operation must not exceed 8; for example, 4 times for main array (X8 device:1time/512byte, X16 device:1time  
256word) and 4 times for spare array (X8 device:1time/16byte ,X16 device:1time/8word).  
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading  
period in which up to 2112 bytes (X8 device) or 1056 words (X16 device) of data may be loaded into the data register,  
followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.  
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle  
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The  
device supports random data input in a page. The column address of next data, which will be entered, may be  
changed to the address which follows random data input command (85h). Random data input may be operated multi-  
ple times regardless of how many times it is done in a page.  
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously  
entering the serial data will not initiate the programming process. The P/E/R controller automatically executes the  
algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once  
the program process starts, the Read Status Register command may be entered to read the status register. The system  
controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the  
Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When  
the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only  
errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command  
mode until another valid command is written to the command register. Figure 14 details the sequence.  
Rev 0.4 / Jun. 2007  
12  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
3.3 Block Erase.  
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase  
Setup command (60h). Only address A18 to A27 (X8) or A17 to A26 (X16) is valid while A12 to A17 (X8) or A11 to A16  
(X16) are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing  
process. This two-step sequence of setup followed by execution command ensures that memory contents are not acci-  
dentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the P/  
E/R controller handles erase and erase-verify. Once the erase process starts, the Read Status Register command may be  
entered to read the status register. The system controller can detect the completion of an erase by monitoring the R/B  
output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid  
while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure  
18 details the sequence.  
3.4 Copy-Back Program.  
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an exter-  
nal memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system perfor-  
mance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also  
need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential  
execution of page-read without serial access and copyingprogram with the address of destination page. A read opera-  
tion with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or 1056word (X16  
device) data into the internal data buffer.  
As soon as the device returns to Ready state, Copy Back command (85h) with the address cycles of destination page  
may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data  
input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 16.  
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if  
Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external  
error detection/correction scheme. For this reason, two bit error correction is recommended for the use  
of Copy-Back operation."  
Figure 16 shows the command sequence for the copy-back operation.  
The Copy Back Program operation requires three steps:  
1. The source page must be read using the Read A command (one bus write cycle to setup the command and then  
4 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page  
Buffer.  
2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is  
given with the 4bus cycles to input the target page address.  
3. Then the confirm command is issued to start the P/E/R Controller.  
Note:  
1. On the same plane.  
2. It’s prohibited to operate copy-back program from an odd address page (source page) to an even address page  
(target page) or from an even address page (source page) to an odd address page (target page).  
Therefore, the copy-back program is permitted just between odd address pages or even address pages.  
Rev 0.4 / Jun. 2007  
13  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
3.5 Read Status Register.  
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-  
pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-  
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,  
whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory  
connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer  
to Table 14 for specific Status Register definitions, and Figure 10 for specific timings requirements . The command reg-  
ister remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read dur-  
ing a random read cycle, the read command (00h) should be given before starting read cycles.  
3.6 Read ID.  
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an  
address input of 00h. Four read cycles sequentially output the 1st cycle (ADh), and 2nd cycle (the device code) and  
3rd cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are  
issued to it. Figure 19 shows the operation sequence, while Tables 16 explain the byte meaning.  
3.7 Reset.  
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state  
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory  
cells being altered are no longer valid, as the data will be partially programmed or erased.  
The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when  
WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset  
command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset com-  
mand is written.  
Rev 0.4 / Jun. 2007  
14  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
3.8 Cache program  
Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16  
device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data  
input may be executed while data stored in data register are programmed into memory cell. After writing the first set  
of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program com-  
mand (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program  
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period  
of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started  
with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers  
become ready by polling the Cache- Busy status bit (I/O 6). Pass/fail status of only the previous page is available  
upon the return to Ready state.  
When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of pending  
internal programming. The programming of the cache registers is initiated only when the pending program cycle is  
finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for  
internal Ready/Busy may be polled to identify the completion of internal programming.  
If the system monitors the progress of programming only with R/B, the last page of the target programming sequence  
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used  
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting  
other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous  
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready  
(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is  
checked. See Fig. 18 for more details.  
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program.  
However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page  
is initiated only after completion of the previous cycle, which can be expressed as the following formula.  
tPROG=Program time for the last page + Program time for the (last-1)page  
- (Program command cycle time + Last page data loading time)  
Rev 0.4 / Jun. 2007  
15  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
3.9 Cache Read  
Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st  
latency end, while user can start reading out data, device internally starts reading following page.  
Start address of 1st page must be at page start (A<10:0>=00h) : in this way after 1st latency time (tr) , automatic  
data download will be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for  
x8 device (50us for x16 device).  
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache  
read) user can check operation status using :  
- R/B ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device in  
ternally is active on n+1 page  
- Status register (SR<6> behave like R/B, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)  
To exit cache read operation, a cache read exit command (34h) must be issued. This command can be given any time  
(both device idle and reading).  
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time  
shorter then tCBSY before becoming again idle and ready to accept any further commands. Figure 17 describes how  
to handle Cache Read through Status register .  
If user reads last byte/word of the memory array, then he has to stop by giving a cache read exit command. In general,  
if user wants to terminate a cache read, then he must give a cache read exit command (or reset command) before  
starting any new operation.  
Random data output is not available in cache read.  
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.  
Rev 0.4 / Jun. 2007  
16  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
4. OTHER FEATURES  
4.1 Data Protection for Power on/off Sequence  
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal  
voltage detector disables all functions whenever Vcc is below about 2.0V (3.3V version). WP pin provides hardware  
protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us  
is required before internal circuit gets ready for any command sequences as shown in Figure 24. The two-step com-  
mand sequence for program/erase provides additional software protection.  
If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed  
the data. Power protection function is only available during the power on/off sequence.  
4.2 Ready/Busy.  
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,  
copy-back, cache program and random read completion. The R/B pin is normally high and goes to low when the device  
is busy (after a reset, read, program, erase operation). It returns to high when the P/E/R controller has finished the  
operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up  
resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with  
the following reference chart (Figure 25). Its value can be determined by the following guidance.  
Rev 0.4 / Jun. 2007  
17  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Valid Block Number  
NVB  
1004  
1024  
Blocks  
Table 7: Valid Blocks Number  
NOTE:  
1. The 1st block is guaranteed to be a valid block up to 1K cycles with ECC. (1bit/528bytes)  
Value  
3.3V  
Symbol  
Parameter  
Unit  
Ambient Operating Temperature (Temperature Range Option 1)  
Ambient Operating Temperature (Industrial Temperature Range)  
Temperature Under Bias  
0 to 70  
V
TA  
-40 to 85  
-50 to 125  
-65 to 150  
-0.6 to 4.6  
-0.6 to 4.6  
TBIAS  
TSTG  
Storage Temperature  
(2)  
Input or Output Voltage  
VIO  
Vcc  
Supply Voltage  
V
Table 8: Absolute maximum ratings  
NOTE:  
1. Except for the rating “Operating Temperature Range, stresses above those listed in the Table “Absolute  
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of  
the device at these or any other conditions above those indicated in the Operating sections of this specification is  
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.  
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.  
Rev 0.4 / Jun. 2007  
18  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
$???a?$?  
$''5(66  
5(*,67(5?  
&2817(5  
352*5$0  
(5$6(  
;
&21752//(5  
+9?*(1(5$7,21  
?????0ELW?????0ELW  
1$1'?)ODVK  
0(025<?$55$<  
'
(
&
2
'
(
5
$/(  
&/(  
:(  
&(  
:3  
&200$1'  
,17(5)$&(  
/2*,&  
5(  
3$*(?%8))(5  
<?'(&2'(5  
&200$1'  
5(*,67(5  
'$7$  
5(*,67(5  
%8))(56  
,2  
Figure 5: Block Diagram  
Rev 0.4 / Jun. 2007  
19  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
3.3Volt  
Parameter  
Symbol  
Test Conditions  
Unit  
Min  
Typ  
Max  
tRC=30ns  
CE=VIL,  
IOUT=0mA  
Sequential  
Read  
ICC1  
-
15  
30  
mA  
Operating  
Current  
Program  
Erase  
ICC2  
ICC3  
-
-
-
-
15  
15  
30  
30  
mA  
mA  
CE=VIH,  
WP=0V/Vcc  
Stand-by Current (TTL)  
Stand-by Current (CMOS)  
ICC4  
-
-
1
mA  
uA  
CE=Vcc-0.2,  
WP=0V/Vcc  
ICC5  
ILI  
10  
50  
Input Leakage Current  
Output Leakage Current  
Input High Voltage  
VIN=0 to Vcc (max)  
-
-
-
-
-
-
-
uA  
uA  
V
± 10  
± 10  
Vcc+0.3  
Vccx0.2  
-
ILO  
VIH  
VIL  
VOUT =0 to Vcc (max)  
-
Vccx0.8  
-0.3  
2.4  
-
Input Low Voltage  
-
V
Output High Voltage Level  
Output Low Voltage Leve  
VOH  
VOL  
IOH=-400uA  
IOL=2.1mA  
V
-
0.4  
V
IOL  
(R/B)  
Output Low Current (R/B)  
VOL=0.4V  
8
10  
-
mA  
Table 9: DC and Operating Characteristics  
Value  
3.3Volt  
0V to Vcc  
5ns  
Parameter  
Input Pulse Levels  
Input Rise and Fall Times  
Input and Output Timing Levels  
Output Load (2.7V - 3.6V)  
Vcc / 2  
1 TTL GATE and CL=50pF  
Table 10: AC Conditions  
Rev 0.4 / Jun. 2007  
20  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Item  
Input / Output Capacitance  
Input Capacitance  
Symbol  
CI/O  
Test Condition  
VIL=0V  
Min  
Max  
10  
Unit  
pF  
-
-
CIN  
VIN=0V  
10  
pF  
Table 11: Pin Capacitance (TA=25C, F=1.0MHz)  
Parameter  
Symbol  
tPROG  
tCBSY  
Min  
Typ  
Max  
700  
700  
4
Unit  
Program Time  
-
-
-
-
-
200  
us  
us  
Dummy Busy Time for Cache Program  
Number of partial Program Cycles in the same page  
Block Erase Time  
3
-
Main Array  
Spare Array  
NOP  
Cycles  
Cycles  
ms  
NOP  
-
4
tBERS  
2
3
Table 12: Program / Erase Characteristics  
Rev 0.4 / Jun. 2007  
21  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
3.3Volt  
Parameter  
Symbol  
Unit  
Min  
15  
5
Max  
CLE Setup time  
tCLS  
tCLH  
tCS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
CLE Hold time  
CE setup time  
20  
5
CE hold time  
tCH  
WE pulse width  
tWP  
tALS  
tALH  
15  
15  
5
ALE setup time  
ALE hold time  
(4)  
Address to Data Loading  
Data setup time  
100  
5
tADL  
tDS  
tDH  
tWC  
tWH  
tR  
Data hold time  
5
Write Cycle time  
30  
10  
WE High hold time  
Data Transfer from Cell to register  
ALE to RE Delay  
25  
tAR  
15  
15  
20  
15  
CLE to RE Delay  
tCLR  
tRR  
Ready to RE Low  
RE Pulse Width  
tRP  
WE High to Busy  
Read Cycle Time  
tWB  
tRC  
100  
30  
RE Access Time  
tREA  
tRHZ  
tCHZ  
tREH  
tIR  
20  
50  
50  
RE High to Output High Z  
CE High to Output High Z  
RE High Hold Time  
Output High Z to RE low  
CE Access Time  
10  
0
tCEA  
tWHR  
tOH  
25  
WE High to RE low  
RE or CE High to Output Hold  
60  
10  
(1)  
Device Resetting Time (Read / Program / Erase)  
tRST  
5/10/500  
(3)  
Write Protection time  
100  
ns  
tWW  
Table 13: AC Timing Characteristics  
NOTE:  
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us  
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.ting time.  
3. Program / Erase Enable Operation : WP high to WE High.  
Program / Erase Disable Operation : WP Low to WE High.  
4. tADL is the time from the WE rising edge of final address cycle to the WE rising of first data cycle.  
Rev 0.4 / Jun. 2007  
22  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Pagae  
Program  
Block  
Erase  
Cache  
Program  
Cache  
Read  
IO  
Read  
CODING  
0
1
2
3
4
Pass / Fail  
Pass / Fail  
Pass / Fail (N)  
NA  
NA  
NA  
NA  
NA  
Pass: ‘0’ Fail: ‘1’  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Pass / Fail (N-1)  
Don’t care  
NA  
NA  
NA  
-
-
-
P/E/R  
Controller Bit  
P/E/R  
Controller Bit  
5
6
7
Ready/Busy  
Ready/Busy  
Write Protect  
Ready/Busy  
Ready/Busy  
Write Protect  
Ready/Busy  
Ready/Busy  
Write Protect  
Active: ‘0’ Idle: ‘1’  
Busy: ‘0’ Ready’: ‘1’  
Cache Register  
Free  
Ready/Busy  
Protected: ‘0’ Not  
Protected: ‘1’  
Write Protect  
Table 14: Status Register Coding  
DEVIIDENTIFIER CYCLE  
DESCRIPTION  
1st  
Manufacturer Code  
Device Identifier  
2nd  
Internal chip number, cell Type, Number of Simultaneously Programmed  
pages.  
3rd  
4th  
Page size, spare size, Block size, Organization  
Table 15: Device Identifier Coding  
1st cycle  
2nd cycle  
Part Number  
Voltage Bus Width  
3rd Code 4th Code  
(Manufacture Code) (Device Code)  
HY27UF081G2A  
HY27UF161G2A  
3.3V  
3.3V  
x8  
ADh  
ADh  
F1h  
C1h  
80h  
80h  
1Dh  
5Dh  
x16  
Table 16: Read ID Data Table  
Rev 0.4 / Jun. 2007  
23  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Description  
IO7  
IO6  
IO5 IO4  
IO3 IO2  
IO1 IO0  
1
2
4
0 0  
0 1  
1 0  
1 1  
Die / Package  
String Type  
Reserved  
Single Level  
2x Multi-level  
Reserved  
0 0  
0 1  
1 0  
1 1  
Reservedl  
1
2
3
4
0 0  
0 1  
1 0  
1 1  
Number of  
Simultaneously  
Programmed Pages  
Interleave Program  
Between different dice  
Not Support  
Support  
0
1
Not Support  
Support  
0
1
Write Cache  
Table 17: 3rd Byte of Device Idendifier Description  
Description  
1KB  
2KB  
4KB  
Reserved  
IO7  
IO6  
IO5-4  
IO3  
IO2  
IO1-0  
0 0  
0 1  
1 0  
1 1  
Page Size  
(Without Spare Area)  
Spare Area Size  
(Byte / 512 Byte)  
8
16  
0
1
50ns  
30ns  
25ns  
Reserved  
0
0
1
1
0
1
0
1
Serial Access Time  
0 0  
0 1  
1 0  
1 1  
64KB  
128KB  
256KB  
512KB  
Block Size (Without  
Spare Area)  
X8  
X16  
0
1
Organization  
Table 18: 4th Byte of Device Identifier Description  
Rev 0.4 / Jun. 2007  
24  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
W&/  
6
W&/+  
W&+  
&/(  
W&6  
&(  
W:3  
:(  
W$/6  
W$/+  
$/(  
W'6  
W'+  
,?2?[  
&RPPDQG  
Figure 6: Command Latch Cycle  
W&/6  
W&6  
&/(  
&(  
W:&  
W:&  
W:&  
W:3  
W:3  
W:3  
W:3  
:(  
W:+  
W:+  
W:+  
W$/6  
W$/6  
W$/6  
W$/+  
W$/+  
W$/+  
W$/+  
W'+  
W$/6  
$/(  
W'+  
W'+  
W'+  
W'6  
W'6  
W'6  
W'6  
,?2[  
&RO??$GG?  
&RO??$GG?  
5RZ?$GG?  
5RZ?$GG?  
Figure 7: Address Latch Cycle  
Rev 0.4 / Jun. 2007  
25  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
W&/+  
W&+  
&/(  
&(  
W:&  
$/(  
W$/6  
W:3  
W:3  
W:3  
:(  
W:+  
W'+  
W'+  
W'+  
',1??  
W'6  
W'6  
',1?ILQDO?  
W'6  
',1??  
,?2[  
Figure 8. Input Data Latch Cycle  
t
CEA  
CE  
t
CHZ*  
t
REH  
t
REA  
t
REA  
tREA  
t
OH  
t
RP  
RE  
t
RHZ  
t
RHZ*  
OH  
t
I/Ox  
Dout  
Dout  
Dout  
t
RR  
t
RC  
R/B  
Notes : Transition is measured ±±22m? from steady state voltage with load.  
This parameter is sampled and not 122% tested.  
Figure 9: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)  
Rev 0.4 / Jun. 2007  
26  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
tCLR  
CLE  
CE  
tCLS  
tCS  
tCLH  
tCH  
tWP  
WE  
tCEA  
t2H  
tCHZ  
tWHR  
RE  
t2H  
tDH  
tREA  
tDS  
72h  
tIR  
tRH=  
I/Ox  
Status Output  
Figure 10: Status Read Cycle  
W
&/5  
&/(  
&(  
W
:&  
:(  
$/(  
W
:%  
W
$5  
W
5+=  
W
5
W
5&  
5(  
W
55  
&RO?$GG? &RO?$GG? 5RZ?$GG? 5RZ?$GG?  
&ROXPQ?$GGUHVV 5RZ?$GGUHVV  
'RXW?1  
'RXW?1?  
'RXW?0  
??K  
??K  
,?2[  
%XV\  
5?'  
Figure 11: Read1 Operation (Read One Page)  
Rev 0.4 / Jun. 2007  
27  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
&/(  
&(  
:(  
W:%  
W&+=  
W$5  
W2+  
$/(  
W5  
W5&  
5(  
W55  
??K  
&RO??$GG? &RO??$GG?  
&ROXPQ?$GGUHVV  
5RZ?$GG? 5RZ?$GG?  
5RZ?$GGUHVV  
??K  
'RXW?1  
'RXW?1??  
'RXW?1??  
,?2[  
5?%  
%XV\  
Figure 12: Read1 Operation intercepted by CE  
Rev 0.4 / Jun. 2007  
28  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Figure 13 : Random Data output  
Rev 0.4 / Jun. 2007  
29  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
&/(  
&(  
W:&  
W:&  
W:&  
:(  
W:%  
W352*  
W$'/  
$/(  
5(  
'LQ  
1
'LQ  
0
,?2[  
&RO??$GG? &RO??$GG? 5RZ?$GG? 5RZ?$GG?  
5RZ?$GGUHVV  
??K  
??K  
,?2R  
??K  
6HULDO?'DWD  
5HDG?6WDWXV  
&RPPDQG  
3URJUDP  
??XS?WR?P?%\WH  
,QSXW?&RPPDQG  
&ROXPQ?$GGUHVV  
&RPPDQG  
6HULDO?,QSXW  
5?%  
;??GHYLFH???P? ?????E\WH  
;???GHYLFH???P? ?????ZRUG  
,?2R ??6XFFHVVIXO?3URJUDP  
,?2R ??(UURU?LQ?3URJUDP  
1RWH???W$'/?LV?WKH?WLPH?IURP?WKH?:(?ULVLQJ?HGJH?RI?ILQDO?DGGUHVV?F\FOH?WR?WKH?:(?ULVLQJ?HGJH?RI?ILUVW?GDWD?F\FOH?  
Figure 14: Page Program Operation  
Rev 0.4 / Jun. 2007  
30  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Figure 15 : Random Data In  
Rev 0.4 / Jun. 2007  
31  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Figure 16 : Copy Back Program  
Rev 0.4 / Jun. 2007  
32  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Figure 17 : Cache Program  
Rev 0.4 / Jun. 2007  
33  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
&/(  
&(  
W:&  
:(  
W:%  
W%(56  
$/(  
5(  
??K  
'?K  
,?2  
[
5RZ?$GG?5RZ?$GG?  
5RZ?$GGUHVV  
??K  
,?2?  
5?%  
%86<  
$XWR?%ORFN?(UDVH?6HWXS  
&RPPDQG  
(UDVH?&RPPDQG  
5HDG?6WDWXV ,?2? ??6XFFHVVIXO?(UDVH  
&RPPDQG  
,?2? ??(UURU?LQ?(UDVH  
Figure 18: Block Erase Operation (Erase One Block)  
&/(  
&(  
:(  
W$5??  
$/(  
5(  
W5($??  
??K  
?'K  
)?K  
??K  
??K  
$'K  
,?2?[  
5HDG?,'?&RPPDQG $GGUHVV???F\FOH  
?VW?F\FOH  
?QG?F\FOH  
?UG?F\FOH  
?WK?F\FOH  
Figure 19: Read ID Operation  
Rev 0.4 / Jun. 2007  
34  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
&/(  
$/(  
:(?  
'?  
'? '? '? '?  
??K $GG? $GG? $GG? $GG? ??K  
????  
'? '? '? '? '?  
????  
'?  
'? '?  
???V  
5(?  
5HDG??UG?SDJH  
5HDG??WK?SDJH  
5HDG??VW?SDJH 5HDG??QG?SDJH  
,GOH  
,GOH  
,QWHUQDO?RSHUDWLRQ  
???V  
???V  
???V  
????V  
????V  
????V  
6WDWXV?5HJLVWHU  
65???????!  
??  
??  
??  
??  
??  
??  
Figure 20: start address at page start :after 1st latency uninterrupted data flow  
Rev 0.4 / Jun. 2007  
35  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
System Interface Using CE don’t care  
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.  
So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND  
Flash to make CE don’t care read operation was disabling of the automatic sequential read function.  
&/(  
&(?GRQ?W?FDUH  
&(  
:(  
$/(  
??K  
6WDUW?$GG???&\FOH?  
'DWD?,QSXW  
'DWD?,QSXW  
??K  
,?2[  
Figure 21: Program Operation with CE don’t-care.  
&/(  
&(  
,I?VHTXHQWLDO?URZ?UHDG?HQDEOHG?  
&(?PXVW?EH?KHOG?ORZ?GXULQJ?W5?  
&(?GRQ?W?FDUH  
5(  
$/(  
5?%  
W5  
:(  
,?2[  
??K  
6WDUW?$GG???&\FOH?  
??K  
'DWD?2XWSXW?VHTXHQWLDO?  
Figure 22: Read Operation with CE don’t-care.  
Rev 0.4 / Jun. 2007  
36  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
:(  
$/(  
&/(  
5(  
,2???  
5?%  
))K  
W
567  
Figure 23: Reset Operation  
9FF  
97+  
W
:3  
:(  
??XV  
Figure 24: Power On and Data Protection Timing  
VTH = 2.5 Volt for 3.3 Volt Supply devices  
Rev 0.4 / Jun. 2007  
37  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
5S  
LEXV\  
9FF  
5HDG\  
9FF  
5?%  
???9  
RSHQ?GUDLQ?RXWSXW  
???9  
%XV\  
WI  
WU  
*1'  
'HYLFH  
??)LJ??5S?YV?WU??WI???5S?YV?LEXV\  
#?9FF? ????9??7D? ????&??&  ???S)  
/
???  
???  
LEXV\  
???  
???  
???Q  
???Q  
???Q  
?P  
????  
???  
?P  
?P  
??  
?????  
???  
???  
?N  
???  
?N  
???  
WI  
?N  
?N  
5S??RKP?  
5S?YDOXH?JXLGHQFH  
9FF??0D[?????92/??0D[??  
???9  
5S??PLQ??  
 
,2/????,  
/
?P$????,  
/
ZKHUH?,/?LV?WKH?VXP?RI?WKH?LQSXW?FXUUQWV?RI?DOO?GHYLFHV?WLHG?WR?WKH?5?%?SLQ?  
5S?PD[??LV?GHWHUPLQHG?E\?PD[LPXP?SHUPLVVLEOH?OLPLW?RI?WU  
Figure 25: Ready/Busy Pin electrical specifications  
Rev 0.4 / Jun. 2007  
38  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Bad Block Management  
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the  
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and  
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks  
erased(FFh).  
The Bad Block Information is written prior to shipping. Any block where the 1st Byte/ 1st Word in the spare area of the  
1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read  
before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the  
Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart  
shown in Figure 26. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.  
Block Replacement  
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying  
the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give  
errors in the Status Register.  
As the failure of a page program operation does not affect the data in other pages in the same block, the block can be  
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.  
The Copy Back Program command can be used to copy the data to a valid block.  
See the “Copy Back Program” section for more details.  
Refer to Table 19 for the recommended procedure to follow if an error occurs during an operation.  
Operation  
Erase  
Recommended Procedure  
Block Replacement  
Program  
Read  
Block Replacement or ECC (with 1bit/528byte)  
ECC (with 1bit/528byte)  
Table 19: Block Failure  
67$57  
%ORFN?$GGUHVV  
%ORFN??  
,QFUHPHQW  
%ORFN?$GGUHVV  
8SGDWH  
%DG?%ORFN?WDEOH  
'DWD  
 ))K"  
1R  
1R  
<HV  
/DVW  
EORFN"  
<HV  
(1'  
Figure 26: Bad Block Management Flowchart  
Rev 0.4 / Jun. 2007  
39  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Write Protect Operation  
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations  
are enabled and disabled as follows (Figure 27~30)  
:(  
W
::  
??K  
,?2[  
??K  
5?%  
Figure 27: Enable Programming  
:(  
W
::  
??K  
??K  
,?2[  
5?%  
Figure 28: Disable Programming  
Rev 0.4 / Jun. 2007  
40  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
:(  
W
::  
??K  
'?K  
,?2[  
5?%  
Figure 29: Enable Erasing  
:(  
W
::  
??K  
,?2[  
'?K  
5?%  
Figure 30: Disable Erasing  
Rev 0.4 / Jun. 2007  
41  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
??  
H
$?  
$
'
%
/
?
$?  
??  
??  
',(  
(?  
(
&
&3  
Figure 31: 48pin-TSOP1, 12 x 20mm, Package Outline  
millimeters  
Symbol  
Min  
Typ  
Max  
1.200  
0.150  
1.030  
0.250  
0.200  
0.100  
12.120  
20.100  
18.500  
A
A1  
A2  
B
0.050  
0.980  
0.170  
0.100  
C
CP  
D
11.910  
19.900  
18.300  
12.000  
20.000  
18.400  
0.500  
E
E1  
e
L
0.500  
0
0.680  
5
alpha  
Table 20: 48pin-TSOP1, 12 x 20mm, Package Mechanical Data  
Rev 0.4 / Jun. 2007  
42  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
$
$?  
(
$?  
'
?
&3  
&?  
Figure 32. 48pin-USOP1, 12 x 17mm, Package Outline  
millimeters  
Symbol  
Min  
Typ  
Max  
0.650  
0.080  
0.570  
0.230  
0.175  
0.750  
0.100  
17.100  
12.120  
15.500  
A
A1  
A2  
B
0
0.050  
0.520  
0.160  
0.100  
0.650  
0.470  
0.130  
0.065  
0.450  
C
C1  
CP  
D
16.900  
11.910  
15.300  
17.000  
12.000  
15.400  
0.500  
D1  
E
e
alpha  
0
8
Table 21: 48pin-USOP1, 12 x 17mm, Package Mechanical Data  
Rev 0.4 / Jun. 2007  
43  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
'
'?  
'?  
6'  
)'?  
)'  
H
H
6(  
(
(? (?  
)(  
)(?  
%$//?3FS  
$
H
E
$?  
$?  
Figure 33. 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline  
NOTE: Drawing is not to scale.  
Millimeters  
Typ  
Symbol  
Min  
0.80  
0.25  
0.55  
0.40  
8.90  
Max  
1.00  
0.35  
0.65  
0.50  
9.10  
A
A1  
A2  
b
0.90  
0.30  
0.60  
0.45  
D
9.00  
D1  
D2  
E
E1  
E2  
e
4.00  
7.20  
11.00  
5.60  
8.80  
10.90  
11.10  
0.80  
FD  
FD1  
FE  
FE1  
SD  
SE  
2.50  
0.90  
2.70  
1.10  
0.40  
0.40  
Table 22: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Mechanical Data  
Rev 0.4 / Jun. 2007  
44  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
MARKING INFORMATION - TSOP1/USOP  
Packag  
Marking Exam ple  
K
G
O
2
R
A
TSOP1  
/
H
x
Y
x
2
x
7
x
U
F
x
x
1
USOP  
Y
W
W
x
x
- hynix  
- KOR  
: Hynix Symbol  
: Origin Country  
- HY27UFxx1G2A xxxx  
HY: Hynix  
: Part Number  
27: NAND Flash  
U: Power Supply  
F: Classification  
xx: Bit Organization  
1G: Density  
: U(2.7V~3.6V)  
: Single Level Cell+Single Die+Large Block  
: 08(x8), 16(x16)  
: 1Gbit  
: 1nCE & 1R/nB; Sequential Row Read Disable  
: 2nd Generation  
2: Mode  
A: Version  
: T(48-TSOP1), S(48-USOP)  
: Blank(Normal), P(Lead Free)  
: C(0~70), I(-40~85)  
: B(Included Bad Block), S(1~5 Bad Block),  
P(All Good Block)  
x: Package Type  
x: Package Material  
x: Operating Temperature  
x: Bad Block  
- Y: Year (ex: 5=year 2005, 06= year 2006)  
- ww: Work Week (ex: 12= work week 12)  
- xx: Process Code  
Note  
- Capital Letter  
- Sm all Letter  
: Fixed Item  
: Non-fixed Item  
Rev 0.4 / Jun. 2007  
45  
HY27UF(08/16)1G2A Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
MARKING INFORMATION - FBGA  
Packag  
Marking Exam ple  
K
G
O
2
R
A
H
x
Y
x
2
x
7
x
U
F
0
8
1
FBGA  
Y
W
W
x
x
- hynix  
- KOR  
: Hynix Symbol  
: Origin Country  
- HY27UF081G2A xxxx  
HY: Hynix  
: Part Number  
27: NAND Flash  
U: Power Supply  
F: Classification  
08: Bit Organization  
1G: Density  
: U(2.7V~3.6V)  
: Single Level Cell+Single Die+Large Block  
: 08(x8)  
: 1Gbit  
: 1nCE & 1R/nB; Sequential Row Read Disable  
: 2nd Generation  
2: Mode  
A: Version  
: F(63FBGA)  
x: Package Type  
: Blank(Normal), P(Lead Free)  
: C(0~70), I(-40~85)  
: B(Included Bad Block), S(1~5 Bad Block),  
P(All Good Block)  
x: Package Material  
x: Operating Temperature  
x: Bad Block  
- Y: Year (ex: 5=year 2005, 06= year 2006)  
- ww: Work Week (ex: 12= work week 12)  
- xx: Process Code  
Note  
- Capital Letter  
- Sm all Letter  
: Fixed Item  
: Non-fixed Item  
Rev 0.4 / Jun. 2007  
46  
配單直通車(chē)
HY27UF081G2A-TPIB產(chǎn)品參數(shù)
型號(hào):HY27UF081G2A-TPIB
是否無(wú)鉛: 不含鉛
是否Rohs認(rèn)證: 符合
生命周期:Obsolete
零件包裝代碼:TSOP1
包裝說(shuō)明:TSOP1, TSSOP48,.8,20
針數(shù):48
Reach Compliance Code:compliant
ECCN代碼:3A991.B.1.A
HTS代碼:8542.32.00.51
風(fēng)險(xiǎn)等級(jí):5.81
最長(zhǎng)訪問(wèn)時(shí)間:25000 ns
命令用戶(hù)界面:YES
數(shù)據(jù)輪詢(xún):NO
JESD-30 代碼:R-PDSO-G48
JESD-609代碼:e6
長(zhǎng)度:18.4 mm
內(nèi)存密度:1073741824 bit
內(nèi)存集成電路類(lèi)型:FLASH
內(nèi)存寬度:8
功能數(shù)量:1
部門(mén)數(shù)/規(guī)模:1K
端子數(shù)量:48
字?jǐn)?shù):134217728 words
字?jǐn)?shù)代碼:128000000
工作模式:ASYNCHRONOUS
最高工作溫度:85 °C
最低工作溫度:-40 °C
組織:128MX8
封裝主體材料:PLASTIC/EPOXY
封裝代碼:TSOP1
封裝等效代碼:TSSOP48,.8,20
封裝形狀:RECTANGULAR
封裝形式:SMALL OUTLINE, THIN PROFILE
頁(yè)面大?。?/td>2K words
并行/串行:PARALLEL
峰值回流溫度(攝氏度):260
電源:3.3 V
編程電壓:3.3 V
認(rèn)證狀態(tài):Not Qualified
就緒/忙碌:YES
座面最大高度:1.2 mm
部門(mén)規(guī)模:128K
最大待機(jī)電流:0.00005 A
子類(lèi)別:Flash Memories
最大壓擺率:0.03 mA
最大供電電壓 (Vsup):3.6 V
最小供電電壓 (Vsup):2.7 V
標(biāo)稱(chēng)供電電壓 (Vsup):3.3 V
表面貼裝:YES
技術(shù):CMOS
溫度等級(jí):INDUSTRIAL
端子面層:TIN BISMUTH
端子形式:GULL WING
端子節(jié)距:0.5 mm
端子位置:DUAL
處于峰值回流溫度下的最長(zhǎng)時(shí)間:20
切換位:NO
類(lèi)型:NAND TYPE
寬度:12 mm
Base Number Matches:1
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