久久久免费看黄A级毛片高清,美女爽到高潮嗷嗷嗷叫免费

HY29LV160

16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory

KEY FEATURES

n Single Power Supply Operation

n 100,000 Write Cycles per Sector Minimum

– Read, program and erase operations from

2.7 to 3.6 volts

– Ideal for battery-powered applications

n High Performance

n Data# Polling and Toggle Bits

– Provide software confirmation of

completion of program and erase

operations

– 70, 80, 90 and 120 ns access time

versions

n Ultra-low Power Consumption (Typical

Values At 5 Mhz)

n Ready/Busy# Pin

– Provides hardware confirmation of

completion of program and erase

operations

– Automatic sleep mode current: 1 μA

– Standby mode current: 1 μA

– Read current: 9 mA

n Hardware Reset Pin (RESET#) Resets the

Device to Reading Array Data

n Compliant With Common Flash Memory

Interface (CFI) Specification

– Program/erase current: 20 mA

n Flexible Sector Architecture:

– One 16 KB, two 8 KB, one 32 KB and

thirty-one 64 KB sectors in byte mode

– One 8 KW, two 4 KW, one 16 KW and

thirty-one 32 KW sectors in word mode

– Top or bottom boot block configurations

available

– Flash device parameters stored directly

on the device

– Allows software driver to identify and use

a variety of different current and future

Flash products

n Compatible With JEDEC standards

– Pinout and software compatible with

single-power supply Flash devices

– Superior inadvertent write protection

n Space Efficient Packaging

– 48-pin TSOP and 48-ball FBGA packages

n Sector Protection

– Allows locking of a sector or sectors to

prevent program or erase operations

within that sector

– Sectors lockable in-system or via

programming equipment

– Temporary Sector Unprotect allows

changes in locked sectors (requires high

voltage on RESET# pin)

LOGIC DIAGRAM

n Fast Program and Erase Times

– Sector erase time: 0.25 sec typical for

each sector

20

8

7

– Chip erase time: 8 sec typical

– Byte program time: 9 μs typical

n Unlock Bypass Program Command

– Reduces programming time when issuing

multiple program command sequences

n Automatic Erase Algorithm Preprograms

and Erases Any Combination of Sectors

or the Entire Chip

n Erase Suspend/Erase Resume

– Suspends an erase operation to allow

reading data from, or programming data

to, a sector that is not being erased

– Erase Resume can then be invoked to

complete suspended erasure

A[19:0]

CE#

DQ[7:0]

DQ[14:8]

OE#

DQ15/A-1

RY/BY#

W E #

RESET#

BYTE#

n Automatic Program Algorithm Writes and

Verifies Data at Specified Addresses

Preliminary

Revision 1.2, May 2001

HY29LV160

GENERAL DESCRIPTION

The HY29LV160 is a 16 Mbit, 3 volt-only, CMOS

Flash memory organized as 2,097,152 (2M) bytes

or 1,048,576 (1M) words that is available in 48-

pin TSOP and 48-ball FBGA packages. Word-

wide data (x16) appears on DQ[15:0] and byte-

wide (x8) data appears on DQ[7:0].

the memory array, while Temporary Sector Un-

protect allows in-system erasure and code

changes in previously protected sectors. Erase

Suspend enables the user to put erase on hold for

any period of time to read data from, or program

data to, any sector that is not selected for era-

sure. True background erase can thus be

achieved. The device is fully erased when shipped

from the factory.

The HY29LV160 can be programmed and erased

in-system with a single 3 volt V_CCsupply. Inter-

nally generated and regulated voltages are pro-

vided for program and erase operations, so that

the device does not require a higher voltage V_PP

power supply to perform those functions. The de-

vice can also be programmed in standard EPROM

programmers. Access times as low as 80 ns over

the full operating voltage range of 2.7 - 3.6 volts,

and 70 ns with a limited voltage range of 3.0 - 3.6

volts, are offered for timing compatibility with the

zero wait state requirements of high speed mi-

croprocessors. To eliminate bus contention, the

HY29LV160 has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

Addresses and data needed for the programming

and erase operations are internally latched during

write cycles, and the host system can detect

completion of a program or erase operation by

observing the RY/BY# pin, or by reading the DQ[7]

(Data# Polling) or DQ[6] (Toggle) status bits. Hard-

ware data protection measures include a low V_CC

detector that automatically inhibits write operations

during power transitions.

After a program or erase cycle has been com-

pleted, or after assertion of the RESET# pin (which

terminates any operation in progress), the device

is ready to read data or to accept another com-

mand. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

The device is compatible with the JEDEC single-

power-supply Flash memory command set stan-

dard. Commands are written to the command reg-

ister using standard microprocessor write timings.

They are then routed to an internal state-machine

that controls the erase and programming circuits.

Device programming is performed a byte/word at

a time by executing the four-cycle Program Com-

mand write sequence. This initiates an internal al-

gorithm that automatically times the program pulse

widths and verifies proper cell margin. Faster pro-

gramming times can be achieved by placing the

HY29LV160 in the Unlock Bypass mode, which

requires only two write cycles to program data in-

stead of four.

Two power-saving features are embodied in the

HY29LV160. When addresses have been stable

for a specified amount of time, the device enters

Automatic Sleep mode. The host can also place

the device into Standby mode. Power consump-

tion is greatly reduced in both of these modes.

Common Flash Memory Interface (CFI)

To make Flash memories interchangeable and to

encourage adoption of new Flash technologies,

major Flash memory suppliers developed a flex-

ible method of identifying Flash memory sizes and

configurations in which all necessary Flash device

parameters are stored directly on the device.

Parameters stored include memory size, byte/word

configuration, sector configuration, necessary volt-

ages and timing information. This allows one set

of software drivers to identify and use a variety of

different current and future Flash products. The

standard which details the software interface nec-

essary to access the device to identify it and to

determine its characteristics is the Common Flash

Memory Interface (CFI) Specification. The

HY29LV160 is fully compliant with this specification.

The HY29LV160’s sector erase architecture allows

any number of array sectors to be erased and re-

programmed without affecting the data contents

of other sectors. Device erasure is initiated by

executing the Erase Command sequence. This

initiates an internal algorithm that automatically

preprograms the array (if it is not already pro-

grammed) before executing the erase operation.

As during programming cycles, the device auto-

matically times the erase pulse widths and veri-

fies proper cell margin. Hardware Sector Protec-

tion optionally disables both program and erase

operations in any combination of the sectors of

Rev. 1.2/May 01

2

HY29LV160

BLOCK DIAGRAM

DQ[15:0]

A[19:0], A-1

DQ[15:0]

STATE

CONTROL

ERASE VOLTAGE

GENERATOR AND

SECTOR SWITCHES

I/O BUFFERS

DATA LATCH

Y-GATING

COMMAND

REGISTER

WE#

CE#

I/O CONTROL

OE#

PROGRAM

VOLTAGE

GENERATOR

BYTE#

RESET#

RY/BY#

Y-DECODER

X-DECODER

A[19:0], A-1

16 Mb FLASH

MEMORY

ARRAY

V_{C C}DETECTOR

TIMER

SIGNAL DESCRIPTIONS

Name

Type

Description

Address, active High. These 20 inputs, combined with the DQ[15]/A[-1] input in

Byte mode, select one location within the array for read or write operations.

A[19:0]

Inputs

Data Bus, active High. These pins provide an 8- or 16-bit data path for read

and write operations. InByte mode, DQ[15]/A[-1] is used as the LSB of the 21-bit

byte address input. DQ[14:8] are unused and remain tri-stated in Byte mode.

DQ[15]/A[-1], Inputs/Outputs

DQ[14:0]

Tri-state

Byte Mode, active Low. Low selects Byte mode, High selects Word mode.

BYTE#

Input

Chip Enable, active Low. This input must be asserted to read data from or

write data to the HY29LV160. When High, the data bus is tri-stated and the

device is placed in the Standby mode.

CE#

OE#

WE#

Input

Output Enable, active Low. Asserted for read operations and negated for

write operations. BYTE# determines whether a byte or a word is read during

the read operation.

Write Enable, active Low. Controls writing of commands or command sequences

in order to program data or erase sectors of the memory array. A write operation

takes place when WE# is asserted while CE# is Low and OE# is High.

Hardware Reset, active Low. Provides a hardware method of resetting the

HY29LV160 to the read array state. When the device is reset, it immediately

terminates any operation in progress. While RESET# is asserted, the device

will be in the Standby mode.

RESET#

Input

Ready/Busy Status. Indicates whether a write or erase command is in

progress or has been completed. Remains Low while the device is actively

programming data or erasing, and goes High when it is ready to read array data.

Output

Open Drain

RY/BY#

3-volt (nominal) power supply.

Power and signal ground.

V_CC

V_SS

--

Rev. 1.2/May 01

3

HY29LV160

PIN CONFIGURATIONS

48-Ball FBGA (Top View, Balls Facing Down)

H6

A6

B6

C6

D6

E6

F6

G6

A[13]

A[12]

A[14]

A[15]

A[16]

BYTE# DQ[15]/A[-1]

V _SS

A5

B5

C5

D5

E5

F5

G5

H5

A[9]

A[8]

A[10]

A[11]

DQ[7]

DQ[14]

DQ[13]

DQ[6]

D4

A4

B4

C4

N C

E4

F4

G4

V _CC

H4

W E #

RESET#

A[19]

DQ[5]

DQ[12]

DQ[4]

D3

N C

A3

B3

N C

C3

E3

F3

G3

H3

RY/BY#

A[18]

DQ[2]

DQ[10]

DQ[11]

DQ[3]

A2

B2

C2

D2

E2

F2

G2

H2

A[7]

A[17]

A[6]

A[5]

DQ[0]

DQ[8]

DQ[9]

DQ[1]

H1

A1

B1

C1

D1

E1

F1

G1

A[3]

A[4]

A[2]

A[1]

A[0]

CE#

OE#

V _SS

A[15]

A[14]

A[13]

A[12]

A[11]

A[10]

A[9]

1

2

3

4

5

6

7

48

47

46

45

44

43

42

A[16]

BYTE#

V_SS

DQ[15]/A[-1]

DQ[7]

DQ[14]

DQ[6]

A[8]

A[19]

8

9

41

40

39

38

37

36

DQ[13]

DQ[5]

NC

10

11

12

13

DQ[12]

DQ[4]

WE#

RESET#

NC

V_{C C}

DQ[11]

TSOP48

NC

RY/BY#

A[18]

A[17]

A[7]

14

15

16

17

18

19

20

35

34

33

32

31

30

29

DQ[3]

DQ[10]

DQ[2]

DQ[9]

DQ[1]

DQ[8]

DQ[0]

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

21

22

23

24

28

27

26

25

OE#

V_SS

CE#

A[0]

Rev. 1.2/May 01

4

HY29LV160

CONVENTIONS

Unless otherwise noted, a positive logic (active

High) convention is assumed throughout this docu-

ment, whereby the presence at a pin of a higher,

more positive voltage (V_IH) causes assertion of the

signal. A ‘#’ symbol following the signal name, e.g.,

RESET#, indicates that the signal is asserted in

the Low state (V_IL). See DC specifications for V_IH

and V_ILvalues.

Whenever a signal is separated into numbered

bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of

bits may also be shown collectively, e.g., as

DQ[7:0].

The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .

. . , E, F) indicates a number expressed in hexadeci-

mal notation. The designation 0bXXXX indicates a

number expressed in binary notation (X = 0, 1).

MEMORY ARRAY ORGANIZATION

Kbytes (4 to 16 Kwords), while the remaining 31

sectors are uniformly sized at 64 Kbytes (32

Kwords). The boot block can be located at the

bottom of the address range (HY29LV160B) or at

the top of the address range (HY29LV160T).

The 16 Mbit Flash memory array is organized into

35 blocks called sectors (S0, S1, . . . , S34). A

sector is the smallest unit that can be erased and

that can be protected to prevent accidental or un-

authorized erasure. See the ‘Bus Operations’ and

‘Command Definitions’ sections of this document

for additional information on these functions.

Tables 1 and 2 define the sector addresses and

corresponding address ranges for the top and bot-

tom boot block versions of the HY29LV160.

In the HY29LV160, four of the sectors, which com-

prise the boot block, vary in size from 8 to 32

BUS OPERATIONS

ware reset to ensure that no spurious alteration of

the memory content occurs during the power tran-

sition. No command is necessary in this mode to

obtain array data, and the device remains enabled

for read accesses until the command register con-

tents are altered.

Device bus operations are initiated through the

internal command register, which consists of sets

of latches that store the commands, along with

the address and data information, if any, needed

to execute the specific command. The command

register itself does not occupy any addressable

memory location. The contents of the command

register serve as inputs to an internal state ma-

chine whose outputs control the operation of the

device. Table 3 lists the normal bus operations,

the inputs and control levels they require, and the

resulting outputs. Certain bus operations require

a high voltage on one or more device pins. Those

are described in Table 4.

This device features an Erase Suspend mode.

While in this mode, the host may read the array

data from any sector of memory that is not marked

for erasure. If the host reads from an address

within an erase-suspended (or erasing) sector, or

while the device is performing a byte or word pro-

gram operation, the device outputs status data

instead of array data. After completing an Auto-

matic Program or Automatic Erase algorithm within

a sector, that sector automatically returns to the

read array data mode. After completing a program-

ming operation in the Erase Suspend mode, the

system may once again read array data with the

same exception noted above.

Read Operation

Data is read from the HY29LV160 by using stan-

dard microprocessor read cycles while placing the

byte or word address on the device’s address in-

puts. The host system must drive the CE# and

OE# pins LOW and drive WE# high for a valid

read operation to take place. The BYTE# pin de-

termines whether the device outputs array data in

words (DQ[15:0]) or in bytes (DQ[7:0]).

The host must issue a hardware reset or the soft-

ware reset command to return a sector to the read

array data mode if DQ[5] goes high during a pro-

gram or erase cycle, or to return the device to the

read array data mode while it is in the Electronic

ID mode.

The HY29LV160 is automatically set for reading

array data after device power-up and after a hard-

Rev. 1.2/May 01

5

HY29LV160

Table 1. HY29LV160T (Top Boot Block) Memory Array Organization

Sector Address ¹

Sect-

Size

Byte Mode

Word Mode

or (KB/KW)

Address Range ²

Address Range ³

A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12]

S0

S1

64/32

32/16

8/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

0x000000 - 0x00FFFF 0x00000 - 0x07FFF

0x010000 - 0x01FFFF 0x08000 - 0x0FFFF

0x020000 - 0x02FFFF 0x10000 - 0x17FFF

0x030000 - 0x03FFFF 0x18000 - 0x1FFFF

0x040000 - 0x04FFFF 0x20000 - 0x27FFF

0x050000 - 0x05FFFF 0x28000 - 0x2FFFF

0x060000 - 0x06FFFF 0x30000 - 0x37FFF

0x070000 - 0x07FFFF 0x38000 - 0x3FFFF

0x080000 - 0x08FFFF 0x40000 - 0x47FFF

0x090000 - 0x09FFFF 0x48000 - 0x4FFFF

0x0A0000 - 0x0AFFFF 0x50000 - 0x57FFF

0x0B0000 - 0x0BFFFF 0x58000 - 0x5FFFF

0x0C0000 - 0x0CFFFF 0x60000 - 0x67FFF

0x0D0000 - 0x0DFFFF 0x68000 - 0x6FFFF

0x0E0000 - 0x0EFFFF 0x70000 - 0x77FFF

0x0F0000 - 0x0FFFFF 0x78000 - 0x7FFFF

0x100000 - 0x10FFFF 0x80000 - 0x87FFF

0x110000 - 0x11FFFF 0x88000 - 0x8FFFF

0x120000 - 0x12FFFF 0x90000 - 0x97FFF

0x130000 - 0x13FFFF 0x98000 - 0x9FFFF

0x140000 - 0x14FFFF 0xA0000 - 0xA7FFF

0x150000 - 0x15FFFF 0xA8000 - 0xAFFFF

0x160000 - 0x16FFFF 0xB0000 - 0xB7FFF

0x170000 - 0x17FFFF 0xB8000 - 0xBFFFF

0x180000 - 0x18FFFF 0xC0000 - 0xC7FFF

0x190000 - 0x19FFFF 0xC8000 - 0xCFFFF

0x1A0000 - 0x1AFFFF 0xD0000 - 0xD7FFF

0x1B0000 - 0x1BFFFF 0xD8000 - 0xDFFFF

0x1C0000 - 0x1CFFFF 0xE0000 - 0xE7FFF

0x1D0000 - 0x1DFFFF 0xE8000 - 0xEFFFF

0x1E0000 - 0x1EFFFF 0xF0000 - 0xF7FFF

0x1F0000 - 0x1F7FFF 0xF8000 - 0xFBFFF

0x1F8000 -0x1F9FFF 0xFC000 - 0xFCFFF

0x1FA000 - 0x1FBFFF 0XFD000 - 0xFDFFF

0x1FC000 - 0x1FFFFF 0xFE000 - 0xFFFFF

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

Notes:

1

8/4

1

0

1

16/8

1

X

1. ‘X’ indicates don’t care.

2. ‘0xN. . . N’ indicates an address in hexadecimal notation.

3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].

Rev. 1.2/May 01

6

HY29LV160

Table 2. HY29LV160B (Bottom Boot Block) Memory Array Organization

Sector Address ¹

Sect- Size

or (KB/KW)

Byte Mode

Word Mode

Address Range ²

Address Range ³

A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12]

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

16/8

8/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

0x000000 - 0x003FFF 0x00000 - 0x01FFF

0x004000 - 0x005FFF 0x02000 - 0x02FFF

0x006000 - 0x007FFF 0X03000 - 0x03FFF

0x008000 - 0x00FFFF 0x04000 - 0x07FFF

0x010000 - 0x01FFFF 0x08000 - 0x0FFFF

0x020000 - 0x02FFFF 0x10000 - 0x17FFF

0x030000 - 0x03FFFF 0x18000 - 0x1FFFF

0x040000 - 0x04FFFF 0x20000 - 0x27FFF

0x050000 - 0x05FFFF 0x28000 - 0x2FFFF

0x060000 - 0x06FFFF 0x30000 - 0x37FFF

0x070000 - 0x07FFFF 0x38000 - 0x3FFFF

0x080000 - 0x08FFFF 0x40000 - 0x47FFF

0x090000 - 0x09FFFF 0x48000 - 0x4FFFF

0x0A0000 - 0x0AFFFF 0x50000 - 0x57FFF

0x0B0000 - 0x0BFFFF 0x58000 - 0x5FFFF

0x0C0000 - 0x0CFFFF 0x60000 - 0x67FFF

0x0D0000 - 0x0DFFFF 0x68000 - 0x6FFFF

0x0E0000 - 0x0EFFFF 0x70000 - 0x77FFF

0x0F0000 - 0x0FFFFF 0x78000 - 0x7FFFF

0x100000 - 0x10FFFF 0x80000 - 0x87FFF

0x110000 - 0x11FFFF 0x88000 - 0x8FFFF

0x120000 - 0x12FFFF 0x90000 - 0x97FFF

0x130000 - 0x13FFFF 0x98000 - 0x9FFFF

0x140000 - 0x14FFFF 0xA0000 - 0xA7FFF

0x150000 - 0x15FFFF 0xA8000 - 0xAFFFF

0x160000 - 0x16FFFF 0xB0000 - 0xB7FFF

0x170000 - 0x17FFFF 0xB8000 - 0xBFFFF

0x180000 - 0x18FFFF 0xC0000 - 0xC7FFF

0x190000 - 0x19FFFF 0xC8000 - 0xCFFFF

0x1A0000 - 0x1AFFFF 0xD0000 - 0xD7FFF

0x1B0000 - 0x1BFFFF 0xD8000 - 0xDFFFF

0x1C0000 - 0x1CFFFF 0xE0000 - 0xE7FFF

0x1D0000 - 0x1DFFFF 0xE8000 - 0xEFFFF

0x1E0000 - 0x1EFFFF 0xF0000 - 0xF7FFF

0x1F0000 - 0x1FFFFF 0xF8000 - 0xFFFFF

8/4

0

1

32/16

64/32

1

X

S10 64/32

S11 64/32

S12 64/32

S13 64/32

S14 64/32

S15 64/32

S16 64/32

S17 64/32

S18 64/32

S19 64/32

S20 64/32

S21 64/32

S22 64/32

S23 64/32

S24 64/32

S25 64/32

S26 64/32

S27 64/32

S28 64/32

S29 64/32

S30 64/32

S31 64/32

S32 64/32

S33 64/32

S34 64/32

Notes:

1. ‘X’ indicates don’t care.

2. ‘0xN. . . N’ indicates an address in hexadecimal notation.

3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0].

Rev. 1.2/May 01

7

HY29LV160

Table 3. HY29LV160 Normal Bus Operations¹

DQ[15:8] ³

Operation

CE#

OE#

WE#

RESET# Address ²DQ[7:0]

BYTE# = H BYTE# = L

Read

Write

L

H

X

H

L

H

A_IN

X

D_OUT

D_IN

D_OUT

D_IN

High-Z

L

H

Output Disable

L

H

X

H

High-Z

CE# Normal Standby

CE# Deep Standby

X

V

_CC± 0.3V

V_CC± 0.3V

X

Hardware Reset

(Normal Standby)

X

L

X

High-Z

Hardware Reset

(Deep Standby)

Notes:

V_SS± 0.3V

1. L = V_IL, H = V_IH, X = Don’t Care (L or H), D_OUT= Data Out, D_IN= Data In. See DC Characteristics for voltage levels.

2. Address is A[19:0, -1] in Byte Mode and A[19:0] in Word Mode.

3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

Table 4. HY29LV160 Bus Operations Requiring High Voltage ^{1, 2}

DQ[15:8]

Operation³

CE# OE# WE# RESET# A[19:12] A[9] A[6] A[1] A[0] DQ[7:0]

BYTE# BYTE#

= H

= L⁵

X

Sector Protect

L

H

L

V_ID

SA⁴

X

L

H

L

D_IN

X

Sector Unprotect

H

X

Temporary Sector

Unprotect ⁶

--

L

--

L

--

H

V_ID

H

--

X

--

L

--

L

--

L

--

X

--

Manufacturer Code

V_ID

0xAD

0x49

0xC4

High-Z

HY29LV160B

Device

L

H

X

V_ID

L

H

0x22 High-Z

Code

HY29LV160T

0x00 =

Unprotected

Sector Protection

Verification

L

H

SA⁴

V_ID

L

H

L

X

High-Z

0x01 =

Protected

Notes:

1. L = V_IL, H = V_IH, X = Don’t Care (L OR H). See DC Characteristics for voltage levels.

2. Address bits not specified are Don’t Care.

3. See text and Appendix A for additional information.

4. SA = Sector Address. See Tables 1 and 2.

5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

6. Normal read, write and output disable operations are used in this mode. See Table 3.

Rev. 1.2/May 01

8

HY29LV160

entered when addresses remain stable for t_ACC

+

Write Operation

30 ns (typical) and is independent of the state of

the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data

when addresses are changed. While in sleep

mode, output data is latched and always available

to the system.

Certain operations, including programming data

and erasing sectors of memory, require the host

to write a command or command sequence to the

HY29LV160. Writes to the device are performed

by placing the byte or word address on the device’s

address inputs while the data to be written is input

on DQ[15:0] (BYTE# = High) or DQ[7:0] (BYTE#

= Low). The host system must drive the CE# and

WE# pins Low and drive OE# High for a valid write

operation to take place. All addresses are latched

on the falling edge of WE# or CE#, whichever

happens later. All data is latched on the rising edge

of WE# or CE#, whichever happens first.

NOTE: Sleep mode is entered only when the device is

in read mode. It is not entered if the device is executing

an automatic algorithm, if it is in erase suspend mode,

or during receipt of a command sequence.

Output Disable Operation

When the OE# input is at V_IH, output data from the

device is disabled and the data bus pins are placed

in the high impedance state.

The “Device Commands” section of this data sheet

provides details on the specific device commands

implemented in the HY29LV160.

Reset Operation

The RESET# pin provides a hardware method of

resetting the device to reading array data. When

the RESET# pin is driven low for the minimum

specified period, the device immediately termi-

nates any operation in progress, tri-states the data

bus pins, and ignores all read/write commands for

the duration of the RESET# pulse. The device also

resets the internal state machine to reading array

data. If an operation was interrupted by the as-

sertion of RESET#, it should be reinitiated once

the device is ready to accept another command

sequence to ensure data integrity.

Standby Operation

When the system is not reading or writing to the

device, it can place the HY29LV160 in the Standby

mode. In this mode, current consumption is greatly

reduced, and the data bus outputs are placed in

the high impedance state, independent of the OE#

input. The Standby mode can be invoked using

two methods.

The device enters the CE# Deep Standby mode

when the CE# and RESET# pins are both held at

V_CC± 0.3V. Note that this is a more restricted

voltage range than V_IH. If both CE# and RESET#

are held at V_IH, but not within V_CC± 0.3V, the de-

vice will be in the CE# Normal Standby mode, but

the standby current will be greater.

Current is reduced for the duration of the RESET#

pulse as described in the Standby Operation sec-

tion above.

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains Low (busy) until

the internal reset operation is complete, which re-

quires a time of t_READY(during Automatic Algo-

rithms). The system can thus monitor RY/BY# to

determine when the reset operation completes,

and can perform a read or write operation t_RBafter

RY/BY# goes High. If RESET# is asserted when

a program or erase operation is not executing (RY/

BY# pin is High), the reset operation is completed

within a time of t_RP. In this case, the host can per-

form a read or write operation t_RHafter the RE-

SET# pin returns High .

The device enters the RESET# Deep Standby

mode when the RESET# pin is held at V_SS± 0.3V.

If RESET# is held at V_ILbut not within V_SS± 0.3V,

the device will be in the RESET# Normal Standby

mode, but the standby current will be greater. See

Reset Operation for additional information.

The device requires standard access time (t_CE) for

read access when the device is in either of the

standby modes, before it is ready to read data. If

the device is deselected during erasure or pro-

gramming, it continues to draw active current until

the operation is completed.

The RESET# pin may be tied to the system reset

signal. Thus, a system reset would also reset the

device, enabling the system to read the boot-up

firmware from the Flash memory.

Sleep Mode

The sleep mode automatically minimizes device

power consumption. This mode is automatically

Rev. 1.2/May 01

9

HY29LV160

Sector Protect Operation

tor, all unprotected sectors must first be protected

prior to the first sector unprotect write cycle. Also,

the unprotect procedure will cause all sectors to

become unprotected, thus, sectors that require

protection must be protected again after the un-

protect procedure is run.

The hardware sector protection feature disables

both program and erase operations in any sector

or combination of sectors. This function can be

implemented either in-system or by using program-

ming equipment.

The method intended for programming equipment

requires a high voltage (V_ID) on address pin A[9]

and the control pins. Refer to the Appendix for

additional information.

The method intended for programming equipment

requires a high voltage (V_ID) on address pin A[9]

and the control pins. Refer to the Appendix at the

end of this document for additional information.

The in-system method requires V_IDonly on the

RESET# pin and uses standard microprocessor

bus cycle timing to implement sector unprotection.

The flow chart in Figure 2 illustrates the algorithm.

The in-system method requires V_IDonly on the

RESET# pin and uses standard microprocessor

bus cycle timing to implement sector protection.

The flow chart in Figure 1 illustrates the algorithm.

The HY29LV160 is shipped with all sectors un-

protected. It is possible to determine whether a

sector is protected or unprotected. See the Elec-

tronic ID Mode section for details.

Temporary Sector Unprotect Operation

This feature allows temporary unprotection of pre-

viously protected sectors to allow changing the

data in-system. Sector Unprotect mode is activated

by setting the RESET# pin to V_ID. While in this

mode, formerly protected sectors can be pro-

grammed or erased by invoking the appropriate

commands (see Device Commands section).

Once V_IDis removed from RESET#, all the previ-

ously protected sectors are protected again. Fig-

ure 3 illustrates the algorithm.

Sector Unprotect Operation

The hardware sector unprotection feature re-en-

ables both program and erase operations in pre-

viously protected sectors. This function can be

implemented either in-system or by using program-

ming equipment. Note that to unprotect any sec-

START

Wait 150 us

RESET# = V_IH

RESET# = V_ID

Write 0x40 to Address

Write Reset Command

Wait 1 us

Read from Address

SECTOR PROTECT

COMPLETE

Write 0x60 to device

NO

YES

Data = 0x01?

TRYCNT = 25?

TRYCNT = 1

NO

YES

Increment TRYCNT

Set Address:

A[19:12] = Sector to Protect

A[6] = 0, A[1] = 1, A[0] = 0

Protect Another

DEVICE FAILURE

NO

Sector?

Write 0x60 to Address

YES

Figure 1. Sector Protect Algorithm

Rev. 1.2/May 01

10

HY29LV160

START

(Note: All sectors must be

protected prior to

unprotecting any sector)

Set Address:

A[19:12] = Sector SNUM

A[6] = 1, A]1] = 1, A]0] = 0

RESET# = V_IH

TRYCNT = 1

SNUM = 0

Write Reset Command

Write 0x40 to Address

Read from Address

SECTOR UNPROTECT

COMPLETE

RESET# = V_ID

Wait 1 us

NO

YES

Data = 0x00?

TRYCNT = 1000?

Write 0x60 to device

NO

YES

Set Address:

A[6] = 1, A]1] = 1, A]0] = 0

Increment TRYCNT

YES

DEVICE FAILURE

SNUM = 34?

Write 0x60 to Address

Wait 15 ms

NO

SNUM = SNUM + 1

Figure 2. Sector Unprotect Algorithm

grammed with its corresponding programming al-

gorithm.

START

Two methods are provided for accessing the Elec-

tronic ID data. The first requires V_IDon address

pin A[9], with additional requirements for obtain-

ing specific data items listed in Table 4. The Elec-

tronic ID data can also be obtained by the host

through specific commands issued via the com-

mand register, as described in the ‘Device Com-

mands’ section of this data sheet.

RESET# = V_ID

(All protected sectors

become unprotected)

Perform Program or Erase

Operations

RESET# = V_IH

(All previously protected

sectors return to protected

state)

While in the high-voltage Electronic ID mode, the

system may read at specific addresses to obtain

certain device identification and status informa-

tion:

TEMPORARY SECTOR

UNPROTECT COMPLETE

?

A read cycle at address 0xXXX00 retrieves the

manufacturer code.

Figure 3. Temporary Sector Unprotect

Algorithm

?

A read cycle at address 0xXXX01 in Word

mode or 0xXXX02 in Byte mode returns the

device code.

Electronic ID Operation (High Voltage Method)

?

A read cycle containing a sector address (SA)

in A[19:12] and the address 0x02 in Word mode

or 0x04 in Byte mode, returns 0x01 if that sec-

tor is protected, or 0x00 if it is unprotected.

The Electronic ID mode provides manufacturer and

device identification and sector protection verifi-

cation through codes output on DQ[15:0]. This

mode is intended primarily for programming equip-

ment to automatically match a device to be pro-

Rev. 1.2/May 01

11

HY29LV160

DEVICE COMMANDS

Table 5. Composition of Command Sequences

Number of Bus Cycles

Command

Device operations are initiated by writing desig-

nated address and data command sequences into

the device. Addresses are latched on the falling

edge of WE# or CE#, whichever happens later.

Data is latched on the rising edge of WE# or CE#,

whichever happens first.

Sequence

Unlock Command

Data

Reset

Read

0

2

1

0

1

0

Note 1

Byte/Word Program

Unlock Bypass

1

0

A command sequence is composed of one, two

or three of the following sub-segments: an unlock

cycle, a command cycle and a data cycle. Table

5 summarizes the composition of the valid com-

mand sequences implemented in the HY29LV160,

and these sequences are fully described in Table

6 and in the sections that follow.

Unlock Bypass

Reset

Unlock Bypass

0

1

Byte/Word Program

Chip Erase

Sector Erase

Erase Suspend

Erase Resume

Electronic ID

CFI Query

4

0

2

0

1

1 (Note 2)

0

Writing incorrect address and data values or writ-

ing them in the improper sequence resets the

HY29LV160 to the Read mode.

0

Note 3

Note 4

Reading Data

The device automatically enters the Read mode

after device power-up, after the RESET# input is

asserted and upon the completion of certain com-

mands. Commands are not required to retrieve

data in this mode. See Read Operation section

for additional information.

Notes:

1. Any number of Flash array read cycles are permitted.

2. Additional data cycles may follow. See text.

3. Any number of Electronic ID read cycles are permitted.

4. Any number of CFI data read cycles are permitted.

?

If DQ[5] (Exceeded Time Limit) goes High dur-

ing a program or erase operation, a Reset com-

mand must be invoked to return the sectors to

the Read mode (or to the Erase Suspend mode

if the device was in Erase Suspend when the

Program command was issued).

Reset Command

Writing the Reset command resets the sectors to

the Read or Erase-Suspend mode. Address bits

are don’t cares for this command.

As described above, a Reset command is not nor-

mally required to begin reading array data. How-

ever, a Reset command must be issued in order

to read array data in the following cases:

The Reset command may also be used to abort

certain command sequences:

?

In a Sector Erase or Chip Erase command se-

quence, the Reset command may be written

at any time before erasing actually begins, in-

cluding, for the Sector Erase command, be-

tween the cycles that specify the sectors to be

erased (see Sector Erase command descrip-

tion). This aborts the command and resets the

device to the Read mode. Once erasure be-

gins, however, the device ignores the Reset

command until the operation is complete.

? If the device is in the Electronic ID mode, a

Reset command must be written to return to

the Read mode. If the device was in the Erase

Suspend mode when the device entered the

Electronic ID mode, writing the Reset command

returns the device to the Erase Suspend mode.

Note: When in the Electronic ID bus operation mode,

the device returns to the Read mode when V_IDis re-

moved from the A[9] pin. The Reset command is not

required in this case.

?

In a Program command sequence, the Reset

command may be written between the se-

quence cycles before programming actually be-

gins. This aborts the command and resets the

device to the Read mode, or to the Erase Sus-

pend mode if the Program command sequence

?

If the device is in the CFI Query mode, a Reset

command must be written to return to the ar-

ray Read mode.

Rev. 1.2/May 01

12

HY29LV160

E l e c t r o n i c I D

6

Rev. 1.2/May 01

13

HY29LV160

Notes for Table 6:

1. All values are in hexadecimal. DQ[15:8] are don’t care for unlock and command cycles.

2. All bus cycles are write operations unless otherwise noted.

3. Address is A[10:0] in Word mode and A[10:0, -1] in Byte mode. A[19:11] are don’t care except as follows:

?

For RA and PA, A[19:11] are the upper address bits of the byte to be read or programmed.

For the sixth cycle of Sector Erase, SA = A[19:12] are the sector address of the sector to be erased.

For the fourth cycle of Sector Protect Verify, SA = A[19:12] are the sector address of the sector to be verified.

4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-

erasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode.

5. The Erase Resume command is valid only during the Erase Suspend mode.

6. The fourth bus cycle is a read cycle.

7. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or in

the CFI Query mode. It must also be issued to return to read mode if DQ[5] goes High during a program or erase

operation. It is not required for normal read operations.

8

This command is valid only when the device is in Read mode or in Electronic ID mode.

9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

is written while the device is in the Erase Sus-

pend mode. Once programming begins, how-

ever, the device ignores the Reset command

until the operation is complete.

should be reinitiated once the reset operation is

complete.

Programming is allowed in any sequence. Only

erase operations can convert a stored “0” to a “1”.

Thus, a bit cannot be programmed from a “0” back

to a “1”. Attempting to do so may halt the opera-

tion and set DQ[5] to “1”, or cause the Data# Poll-

ing algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show

that the data is still “0”.

?

The Reset command may be written between

the cycles in an Electronic ID command se-

quence to abort that command. As described

above, once in the Electronic ID mode, the

Reset command must be written to return to

the array Read mode.

Figure 4 illustrates the programming procedure.

Program Command

The system programs the device a word or byte

at a time by issuing the appropriate four-cycle pro-

gram command sequence as shown in Table 6.

The sequence begins by writing two unlock cycles,

followed by the program setup command and,

lastly, the program address and data. This ini-

tiates the Automatic Program algorithm which au-

tomatically provides internally generated program

pulses and verifies the programmed cell margin.

The host is not required to provide further con-

trols or timings during this operation. When the

Automatic Program algorithm is complete, the de-

vice returns to the array Read mode (or to the

Erase Suspend mode if the device was in Erase

Suspend when the Program command was is-

sued). Several methods are provided to allow the

host to determine the status of the programming

operation, as described in the Write Operation

Status section.

Unlock Bypass/Bypass Program/Bypass Reset

Commands

Unlock bypass provides a faster method for the

host system to program the device. As shown in

Table 6, the Unlock Bypass command sequence

consists of two unlock write cycles followed by a

third write cycle containing the Unlock Bypass

command, 0x20. In the Unlock Bypass mode, a

two-cycle Unlock Bypass Program command se-

quence is used instead of the standard four-cycle

Program sequence to invoke a programming op-

eration. The first cycle in this sequence contains

the Unlock Bypass Program command, 0xA0, and

the second cycle specifies the program address

and data, thus eliminating the initial two unlock

cycles required in the standard Program command

sequence Additional data is programmed in the

same manner.

During the Unlock Bypass mode, only the Unlock

Bypass program and Unlock Bypass Reset com-

mands are valid. To exit the Unlock Bypass mode,

the host must issue the two-cycle Unlock Bypass

Reset command sequence shown in Table 6. The

device then returns to the array Read mode.

Commands written to the device during execution

of the Automatic Program algorithm are ignored.

Note that a hardware reset immediately terminates

the programming operation. To ensure data in-

tegrity, the aborted Program command sequence

Rev. 1.2/May 01

14

HY29LV160

START

Check Programming Status

(See Write Operation Status

Section)

DQ[5] Error Exit

NO

Enable Fast

Programming Verified

Programming?

YES

NO

Last Word/Byte

Done?

Issue UNLOCK BYPASS

Command

YES

Setup Next Address/Data for

Program Operation

NO

Unlock Bypass

Mode?

YES

NO

Unlock Bypass

Mode?

Issue UNLOCK BYPASS

RESET Command

Issue NORMAL PROGRAM

Command

YES

Issue UNLOCK BYPASS

PROGRAM Command

PROGRAMMING

COMPLETE

GO TO ERROR

RECOVERY PROCEDURE

Figure 4. Normal and Unlock Bypass Programming Procedures

Commands written to the device during execution

Chip Erase Command

of the Automatic Erase algorithm are ignored. Note

that a hardware reset immediately terminates the

chip erase operation. To ensure data integrity,

the aborted Chip Erase command sequence

should be reissued once the reset operation is

complete.

The Chip Erase command sequence consists of

two unlock cycles, followed by a set-up command,

two additional unlock cycles and then the Chip

Erase command. This sequence invokes the Au-

tomatic Erase algorithm which automatically

preprograms and verifies the entire memory for

an all zero data pattern prior to electrical erase.

The host system is not required to provide any

controls or timings during these operations.

When the Automatic Erase algorithm is complete,

the device returns to the array Read mode. Sev-

eral methods are provided to allow the host to

determine the status of the erase operation, as

described in the Write Operation Status section.

START

Figure 5 illustrates the chip erase procedure.

Sector Erase Command

Issue CHIP ERASE

Command Sequence

The Sector Erase command sequence consists

of two unlock cycles, followed by the Erase com-

mand, two additional unlock cycles and then the

sector erase data cycle, which specifies the sec-

tor to be erased. As described later in this sec-

tion, multiple sectors can be specified for erasure

with a single command sequence. During sector

erase, all specified sectors are erased sequen-

tially. The data in sectors not specified for era-

sure, as well as the data in any protected sectors,

Check Erase Status

DQ[5] Error Exit

(See Write Operation Status

Section)

Normal Exit

GO TO

CHIP ERASE COMPLETE

ERROR RECOVERY

Figure 5. Chip Erase Procedure

Rev. 1.2/May 01

15

HY29LV160

even if specified for erasure, is not affected by the

sector erase operation.

time that the additional cycles are being issued

and then be re-enabled afterwards.

The Sector Erase command sequence starts the

Automatic Erase algorithm, which preprograms

and verifies the specified unprotected sectors for

an all zero data pattern prior to electrical erase.

The device then provides the required number of

internally generated erase pulses and verifies cell

erasure within the proper cell margins. The host

system is not required to provide any controls or

timings during these operations.

If all sectors specified for erasing are protected,

the device returns to reading array data after ap-

proximately 100 μs. If at least one specified sec-

tor is not protected, the erase operation erases

the unprotected sectors, and ignores the command

for the sectors that are protected.

The system can monitor DQ[3] to determine if the

50 μs sector erase time-out has expired, as de-

scribed in the Write Operation Status section. If

the time between additional sector erase data

cycles can be insured to be less than the time-

out, the system need not monitor DQ[3].

After the sector erase data cycle (the sixth bus

cycle) of the command sequence is issued, a sec-

tor erase time-out of 50 μs, measured from the

rising edge of the final WE# pulse in that bus cycle,

begins. During this time-out window, an additional

sector erase data cycle, specifying the sector ad-

dress of another sector to be erased, may be writ-

ten into an internal sector erase buffer. This buffer

may be loaded in any sequence, and the number

of sectors specified may be from one sector to all

sectors. The only restriction is that the time be-

tween these additional data cycles must be less

than 50 μs, otherwise erasure may begin before

the last data cycle is accepted. To ensure that all

data cycles are accepted, it is recommended that

host processor interrupts be disabled during the

Any command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

then rewrite the command sequence, including any

additional sector erase data cycles. Once the sec-

tor erase operation itself has begun, only the Erase

Suspend command is valid. All other commands

are ignored.

As for the Chip Erase command, note that a hard-

ware reset immediately terminates the sector

erase operation. To ensure data integrity, the

START

Check Erase Status

DQ[5] Error Exit

(See Write Operation Status

Section)

Normal Exit

Write First Five Cycles of

SECTOR ERASE

Command Sequence

GO TO

ERASE COMPLETE

ERROR RECOVERY

Setup First (or Next) Sector

Address for Erase Operation

Write Last Cycle (SA/0x30)

of SECTOR ERASE

Command Sequence

Sectors which require erasure

but which were not specified in

this erase cycle must be erased

later using a new command

sequence

NO

Sector Erase

Time-out (DQ[3])

Expired?

Erase An

Additional Sector?

YES

NO

Figure 6. Sector Erase Procedure

Rev. 1.2/May 01

16

HY29LV160

aborted Sector Erase command sequence should

be reissued once the reset operation is complete.

device exits the Electronic ID mode or the CFI

Query mode, the device reverts to the Erase Sus-

pend mode, and is ready for another valid opera-

tion. See Electronic ID and CFI Query Mode sec-

tions for more information.

When the Automatic Erase algorithm terminates,

the device returns to the array Read mode. Sev-

eral methods are provided to allow the host to de-

termine the status of the erase operation, as de-

scribed in the Write Operation Status section.

The system must write the Erase Resume com-

mand to exit the Erase Suspend mode and con-

tinue the sector erase operation. Further writes of

the Resume command are ignored. Another Erase

Suspend command can be written after the de-

vice has resumed erasing.

Figure 6 illustrates the Sector Erase procedure.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system

to interrupt a sector erase operation to read data

from, or program data in, any sector not being

erased. The command causes the erase opera-

tion to be suspended in all sectors specified for

erasure. This command is valid only during the

sector erase operation, including during the 50 μs

time-out period at the end of the command se-

quence, and is ignored if it is issued during chip

erase or programming operations.

Electronic ID Command

The Electronic ID mode provides manufacturer and

device identification and sector protection verifi-

cation through identifier codes output on DQ[7:0].

This mode is intended primarily for programming

equipment to automatically match a device to be

programmed with its corresponding programming

algorithm.

Two methods are provided for accessing the Elec-

tronic ID data. The first requires V_IDon address

pin A[9], as described previously in the Device

Operations section.

The HY29LV160 requires a maximum of 20 μs to

suspend the erase operation if the Erase Suspend

command is issued during sector erasure. How-

ever, if the command is written during the time-

out, the time-out is terminated and the erase op-

eration is suspended immediately. Once the erase

operation has been suspended, the system can

read array data from or program data to any sec-

tor not specified for erasure. Normal read and

write timings and command definitions apply.

Reading at any address within erase-suspended

sectors produces status data on DQ[7:0]. The host

can use DQ[7], or DQ[6] and DQ[2] together, to

determine if a sector is actively erasing or is erase-

suspended. See the Write Operation Status sec-

tion for information on these status bits.

The Electronic ID data can also be obtained by

the host by invoking the Electronic ID command,

as shown in Table 6. This method does not re-

quire V_ID. The Electronic ID command sequence

may be issued while the device is in the Read

mode or in the Erase Suspend Read mode, that

is, except while programming or erasing.

The Electronic ID command sequence is initiated

by writing two unlock cycles, followed by the Elec-

tronic ID command. The device then enters the

Electronic ID mode, and the system may read at

any address any number of times, without initiat-

ing another command sequence.

After an erase-suspended program operation is

complete, the host can initiate another program-

ming operation (or read operation) within non-sus-

pended sectors. The host can determine the sta-

tus of a program operation during the Erase-Sus-

pended state just as in the standard programming

operation.

?

A read cycle at address 0xXXX00 retrieves the

manufacturer code.

?

A read cycle at address 0xXXX01 in Word

mode or 0xXXX02 in Byte mode returns the

device code.

?

A read cycle containing a sector address (SA)

in A[19:12] and the address 0x02 in A[7:0] in

Word mode (or 0x04 in A[6:0, -1] in Byte mode)

returns 0x01 if that sector is protected, or 0x00

if it is unprotected.

The host may also write the Electronic ID or CFI

Query command sequences when the device is

in the Erase Suspend mode. The device allows

reading Electronic ID and CFI codes even at ad-

dresses within erasing sectors, since the codes

are not stored in the memory array. When the

Rev. 1.2/May 01

17

HY29LV160

The system must write the Reset command to exit

the Electronic ID mode and return to reading ar-

ray data.

The single cycle Query command is valid only

when the device is in the Read mode, including

during Erase Suspend and Standby states and

while in Electronic ID mode, but is ignored other-

wise. Read cycles at appropriate addresses while

in the Query mode provide CFI data as described

later in this section. Write cycles are ignored, ex-

cept for the Reset command.

Query Command and Common Flash Inter-

face (CFI) Mode

The HY29LV160 is capable of operating in the

Common Flash Interface (CFI) mode. This mode

allows the host system to determine the manufac-

turer of the device, its operating parameters, its

configuration and any special command codes that

the device may accept. With this knowledge, the

system can optimize its use of the chip by using

appropriate timeout values, optimal voltages and

commands necessary to use the chip to its full

advantage.

The Reset command returns the device from the

CFI mode to the array Read mode, or to the Erase

Suspend mode if the device was in that mode prior

to entering CFI mode, or to the Electronic ID mode

if the device was in that mode prior to entering

CFI mode. The command is valid only when the

device is in the CFI mode and as otherwise de-

scribed for the normal Reset command.

Tables 7 - 10 specify the data provided by the

HY29LV160 during CFI mode. Data at unspeci-

fied addresses reads out as 0x00. Note that a

value of 0x00 for a data item normally indicates

that the function is not supported. All values in

these tables are in hexadecimal.

Two commands are employed in association with

CFI mode. The first places the device in CFI mode

(Query command) and the second takes it out of

CFI mode (Reset command). These are described

in Table 6.

Table 7. CFI Mode: Identification Data Values

Word Mode

Byte Mode

Description

Address

Data

Address

Data

10

11

12

0051

0052

0059

20

22

24

51

52

59

Query-unique ASCII string "QRY"

Primary vendor command set and control interface ID

code

13

14

0002

0000

26

28

02

00

15

16

0040

0000

2A

2C

40

00

Address for primary algorithm extended query table

Alternate vendor command set and control interface ID

code (none)

17

18

0000

2E

30

00

Address for secondary algorithm extended query table

(none)

19

1A

0000

32

34

00

Rev. 1.2/May 01

18

HY29LV160

Table 8. CFI Mode: System Interface Data Values

Word Mode

Address

Byte Mode

Description

Data

0027

0036

0000

0004

0000

000A

000F

0005

0000

0004

0000

Address

36

Data

27

36

00

04

00

0A

0F

05

00

03

00

V_CCsupply, minimum (2.7V)

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

V_CCsupply, maximum (3.6V)

38

V_PPsupply, minimum (none)

3A

V_PPsupply, maximum (none)

3C

3E

Typical timeout for single word/byte write (2^Nμs)

Typical timeout for maximum size buffer write (2^Nμs)

Typical timeout for individual block erase (2^Nms)

Typical timeout for full chip erase (2^Nms)

Maximum timeout for single word/byte write (2^Nx Typ)

Maximum timeout for maximum size buffer write (2^Nx Typ)

Maximum timeout for individual block erase (2^Nx Typ)

Maximum timeout for full chip erase (not supported)

40

42

44

46

48

4A

4C

Table 9. CFI Mode: Device Geometry Data Values

Word Mode

Byte Mode

Description

Address

Data

Address

Data

Device size (2^Nbytes)

27

0015

4E

15

28

29

0002

0000

50

52

02

00

Flash device interface code (02 = asynchronous x8/x16)

Maximum number of bytes in multi-byte write (not

supported)

2A

2B

0000

54

56

00

Number of erase block regions

2C

0004

58

04

2D

2E

2F

30

0000

0040

0000

5A

5C

5E

60

00

40

00

Erase block region 1 information

[2E, 2D] = # of blocks in region - 1

[30, 2F] = size in multiples of 256-bytes

31

32

33

34

0001

0000

0020

0000

62

64

66

68

01

00

20

00

Erase block region 2 information

Erase block region 3 information

Erase block region 4 information

35

36

37

38

0000

0080

0000

6A

6C

6E

70

00

80

00

39

3A

3B

3C

001E

0000

0001

72

74

76

78

1E

00

01

Rev. 1.2/May 01

19

HY29LV160

Table 10. CFI Mode: Vendor-Specific Extended Query Data Values

Word Mode

Byte Mode

Description

Address

Data

Address

Data

40

41

42

0050

0052

0049

80

82

84

50

52

49

Query-unique ASCII string "PRI"

Major version number, ASCII

43

44

45

46

47

48

49

4A

4B

4C

0031

0030

0000

0002

0001

0004

0000

86

88

8A

8C

8E

90

92

94

96

98

31

30

00

02

01

04

00

Minor version number, ASCII

Address sensitive unlock (0 = required, 1 = not required)

Erase suspend (2 = to read and write

)

Sector protect (N = # of sectors/group)

Temporary sector unprotect (1 = supported)

Sector protect/unprotect scheme (4 = Am29LV800A method)

Simultaneous R/W operation (0 = not supported)

Burst mode type (0 = not supported)

Page mode type (0 = not supported)

0002 (BB)

0003 (TB)

02 (BB)

03 (TB)

Top/bottom boot version (BB = Bottom Boot, TB = Top Boot)

4D

9A

WRITE OPERATION STATUS

device is in Erase Suspend mode. Data# Polling

is valid after the rising edge of the final WE# pulse

in the Program or Erase command sequence.

The HY29LV160 provides a number of facilities to

determine the status of a program or erase op-

eration. These are the RY/BY# (Ready/Busy#)

pin and certain bits of a status word which can be

read from the device during the programming and

erase operations. Table 11 summarizes the sta-

tus indications and further detail is provided in the

subsections which follow.

The system must do a read at the program ad-

dress to obtain valid programming status informa-

tion on this bit. While a programming operation is

in progress, the device outputs the complement

of the value programmed to DQ[7]. When the pro-

gramming operation is complete, the device out-

puts the value programmed to DQ[7]. If a pro-

gram operation is attempted within a protected

sector, Data# Polling on DQ[7] is active for ap-

proximately 1 μs, then the device returns to read-

ing array data.

RY/BY# - Ready/Busy#

RY/BY# is an open-drain output pin that indicates

whether a programming or erase Automatic Algo-

rithm is in progress or has completed. A pull-up

resistor to V_CCis required for proper operation. RY/

BY# is valid after the rising edge of the final WE#

pulse in the corresponding command sequence.

The host must read at an address within any non-

protected sector specified for erasure to obtain

valid erase status information on DQ[7]. During

an erase operation, Data# Polling produces a “0”

on DQ[7]. When the erase operation is complete,

or if the device enters the Erase Suspend mode,

Data# Polling produces a “1” on DQ[7]. If all sec-

tors selected for erasing are protected, Data#

Polling on DQ[7] is active for approximately 100

μs, then the device returns to reading array data.

If at least one selected sector is not protected, the

erase operation erases the unprotected sectors,

and ignores the command for the specified sec-

tors that are protected.

If the output is Low (busy), the device is actively

erasing or programming, including programming

while in the Erase Suspend mode. If the output is

High (ready), the device has completed the op-

eration and is ready to read array data in the nor-

mal or Erase Suspend modes, or it is in the

Standby mode.

DQ[7] - Data# Polling

The Data# (“Data Bar”) Polling bit, DQ[7], indicates

to the host system whether an Automatic Algo-

rithm is in progress or completed, or whether the

Rev. 1.2/May 01

20

HY29LV160

Table 11. Write and Erase Operation Status Summary

1

Mode

Operation

Programming in progress

Programming completed

Erase in progress

DQ[7]

DQ[7]#

Data

0

DQ[6]

Toggle

Data ⁴

Toggle

Data ⁴

DQ[5]

0/1 ²

DQ[3]

N/A

DQ[2]

N/A

RY/BY#

0

1

Data

0/1 ²

Data

1 ³

Data

Normal

Toggle

Data ⁴

0

1

Erase completed ⁵

Data

Read within erase suspended

sector

1

No toggle

Data

0

N/A

Toggle

Data

1

Read within non-erase

suspended sector

Erase

Data

Suspend

Programming in progress ⁶

Programming completed ⁶

DQ[7]#

Data

Toggle

Data ⁴

0/1 ²

N/A

0

1

Data

Notes:

1. A valid address is required when reading status information. See text for additional information.

2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.

3. A ‘1’ during sector erase indicates that the 50 μs time-out has expired and active erasure is in progress. DQ[3] is not

applicable to the chip erase operation.

4. Equivalent to ‘No Toggle’ because data is obtained in this state.

5. Data (DQ[7:0]) = 0xFF immediately after erasure.

6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).

When the system detects that DQ[7] has changed

from the complement to true data (or “0” to “1” for

START

erase), it should do an additional read cycle to read

valid data from DQ[7:0]. This is because DQ[7]

may change asynchronously with respect to the

Read DQ[7:0]

at Valid Address (Note 1)

other data bits while Output Enable (OE#) is as-

Test for DQ[7] = 1?

serted low.

for Erase Operation

DQ[7] = Data?

NO

YES

Figure 7 illustrates the Data# Polling test algorithm.

DQ[6] - Toggle Bit I

Toggle Bit I on DQ[6] indicates whether an Auto-

matic Program or Erase algorithm is in progress

or complete, or whether the device has entered

the Erase Suspend mode. Toggle Bit I may be

read at any address, and is valid after the rising

edge of the final WE# pulse in the Program or

Erase command sequence, including during the

sector erase time-out. The system may use ei-

ther OE# or CE# to control the read cycles.

NO

DQ[5] = 1?

YES

Read DQ[7:0]

at Valid Address (Note 1)

Test for DQ[7] = 1?

for Erase Operation

DQ[7] = Data?

(Note 2)

YES

Successive read cycles at any address during an

Automatic Program algorithm operation (including

programming while in Erase Suspend mode)

cause DQ[6] to toggle. DQ[6] stops toggling when

the operation is complete. If a program address

falls within a protected sector, DQ[6] toggles for

approximately 1 μs after the program command

sequence is written, then returns to reading array

data.

NO

PROGRAM/ERASE

EXCEEDED TIME ERROR

PROGRAM/ERASE

COMPLETE

Notes:

1. During programming , the program address. During sector erase , an

address within any non-protected sector specified for erasure. During

chip erase , an address within any non-protected sector.

2. Recheck DQ[7] since it may change asynchronously to DQ[5].

Figure 7. Data# Polling Test Algorithm

Rev. 1.2/May 01

21

HY29LV160

START

DQ[5] = 1?

YES

Read DQ[7:0]

at Valid Address (Note 1)

NO

Read DQ[7:0]

at Valid Address (Note 1)

Read DQ[7:0]

at Valid Address (Note 1)

YES

NO

DQ[6] Toggled?

(Note 2)

NO

DQ[6] Toggled?

DQ[2] Toggled?

YES

NO

(Note 4)

NO

(Note 3)

YES

PROGRAM/ERASE

COMPLETE

PROGRAM/ERASE

EXCEEDED TIME ERROR

SECTOR BEING READ

IS IN ERASE SUSPEND

SECTOR BEING READ

IS NOT IN ERASE SUSPEND

Notes

:

1. During programming, the program address.

During sector erase, an address within any sector scheduled for erasure.

2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.

3. Use this path if testing for Program/Erase status.

4. Use this path to test whether sector is in Erase Suspend mode.

Figure 8. Toggle Bit I and II Test Algorithm

While the Automatic Erase algorithm is operating,

successive read cycles at any address cause

DQ[6] to toggle. DQ[6] stops toggling when the

erase operation is complete or when the device is

placed in the Erase Suspend mode. The host may

use DQ[2] to determine which sectors are erasing

or erase-suspended (see below). After an Erase

command sequence is written, if all sectors se-

lected for erasing are protected, DQ[6] toggles for

approximately 100 μs, then returns to reading ar-

ray data. If at least one selected sector is not

protected, the Automatic Erase algorithm erases

the unprotected sectors, and ignores the selected

sectors that are protected.

DQ[2] toggles when the host reads at addresses

within sectors that have been specified for era-

sure, but cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ[6],

by comparison, indicates whether the device is ac-

tively erasing or is in Erase Suspend, but cannot

distinguish which sectors are specified for erasure.

Thus, both status bits are required for sector and

mode information.

Figure 8 illustrates the operation of Toggle Bits I

and II.

DQ[5] - Exceeded Timing Limits

DQ[5] is set to a ‘1’ when the program or erase

time has exceeded a specified internal pulse count

limit. This is a failure condition that indicates that

the program or erase cycle was not successfully

completed. DQ[5] status is valid only while DQ[7]

or DQ[6] indicate that the Automatic Algorithm is

in progress.

DQ[2] - Toggle Bit II

Toggle Bit II, DQ[2], when used with DQ[6], indi-

cates whether a particular sector is actively eras-

ing or whether that sector is erase-suspended.

Toggle Bit II is valid after the rising edge of the

final WE# pulse in the command sequence. The

device toggles DQ[2] with each OE# or CE# read

cycle.

The DQ[5] failure condition will also be signaled if

the host tries to program a ‘1’ to a location that is

previously programmed to ‘0’, since only an erase

operation can change a ‘0’ to a ‘1’.

Rev. 1.2/May 01

22

HY29LV160

For both of these conditions, the host must issue

a Reset command to return the device to the Read

mode.

After the initial Sector Erase command sequence

is issued, the system should read the status on

DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to

ensure that the device has accepted the command

sequence, and then read DQ[3]. If DQ[3] is a ‘1’,

the internally controlled erase cycle has begun and

all further sector erase data cycles or commands

(other than Erase Suspend) are ignored until the

erase operation is complete. If DQ[3] is a ‘0’, the

device will accept a sector erase data cycle to mark

an additional sector for erasure. To ensure that

the data cycles have been accepted, the system

software should check the status of DQ[3] prior to

and following each subsequent sector erase data

cycle. If DQ[3] is high on the second status check,

the last data cycle might not have been accepted.

DQ[3] - Sector Erase Timer

After writing a Sector Erase command sequence,

the host may read DQ[3] to determine whether or

not an erase operation has begun. When the

sector erase time-out expires and the sector erase

operation commences, DQ[3] switches from a ‘0’

to a ‘1’. Refer to the “Sector Erase Command”

section for additional information. Note that the

sector erase timer does not apply to the Chip Erase

command.

HARDWARE DATA PROTECTION

The HY29LV160 provides several methods of pro-

tection to prevent accidental erasure or program-

ming which might otherwise be caused by spuri-

ous system level signals during V_CCpower-up and

power-down transitions, or from system noise.

These methods are described in the sections that

follow.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#,

CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by asserting any one of

the following conditions: OE# = V_IL, CE# = V_IH, or

WE# = V_IH. To initiate a write cycle, CE# and WE#

must be a logical zero while OE# is a logical one.

Command Sequences

Commands that may alter array data require a

sequence of cycles as described in Table 6. This

provides data protection against inadvertent writes.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power

up, the device does not accept commands on the

rising edge of WE#. The internal state machine is

automatically reset to the Read mode on power-

up.

Low V_CCWrite Inhibit

To protect data during V_CCpower-up and power-

down, the device does not accept write cycles

when V_CCis less than V_LKO(typically 2.4 volts). The

command register and all internal program/erase

circuits are disabled, and the device resets to the

Read mode. Writes are ignored until V_CCis greater

than V_LKO. The system must provide the proper

signals to the control pins to prevent unintentional

Sector Protection

Additional data protection is provided by the

HY29LV160’s sector protect feature, described

previously, which can be used to protect sensitive

areas of the Flash array from accidental or unau-

thorized attempts to alter the data.

writes when V_CCis greater than V_LKO

.

Rev. 1.2/May 01

23

HY29LV160

ABSOLUTE MAXIMUM RATINGS⁴

Symbol

Parameter

Value

Unit

oC

T_STG

T_BIAS

Storage Temperature

Ambient Temperature with Power Applied

-65 to +150

-55 to +125

oC

Voltage on Pin with Respect to V_SS

VCC¹

:

-0.5 to +4.0

-0.5 to +12.5

-0.5 to V_CC+0.5

V

V_IN2

A[9], OE#, RESET# ²

All Other Pins ¹

I_OS

Output Short Circuit Current ³

200

mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot V_SSto

-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is V_CC+ 0.5 V. During voltage

transitions, input or I/O pins may overshoot to V_CC+2.0 V for periods up to 20 ns. See Figure 10.

2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET#

may undershoot V_SSto –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A[9] is +12.5

V which may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output at a time may be shorted to V_SS. Duration of the short circuit should be less than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these or any other conditions above those indicated in the

operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS¹

Symbol

Parameter

Value

Unit

Ambient Operating Temperature:

T_A

Commercial Temperature Devices

Industrial Temperature Devices

0 to +70

-40 to +85

oC

Operating Supply Voltage:

V_CC

-70, -90V and -12V Versions

All Other Versions

+3.0 to +3.6

+2.7 to +3.6

V

Notes:

1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.

20 ns

V_CC+ 2.0 V

0.8 V

- 0.5 V

V_CC+ 0.5 V

2.0 V

- 2.0 V

20 ns

Figure 9. Maximum Undershoot Waveform

Figure 10. Maximum Overshoot Waveform

Rev. 1.2/May 01

24

HY29LV160

DC CHARACTERISTICS

Parameter

Description

Test Setup²

V_IN= V_SSto V_CC

A[9] = 12.5 V

V_OUT= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

μA

I_LI

I_LIT

I_LO

Input Load Current

A[9] Input Load Current

Output Leakage Current

±1.0

μA

CE# = V_IL,

OE# = V_IH,

Byte Mode

CE# = V_IL,

OE# = V_IH,

Word Mode

CE# = V_IL, OE# = V_IH

CE# = V_CC± 0.3 V,

RESET# = V_CC± 0.3 V

5 MHz

1 MHz

5 MHz

1 MHz

9

2

9

16

4

mA

I_CC1

V_CCActive Read Current ¹

V_CCActive Write Current ^{3, 4}

V_CCCE# Controlled Deep

Standby Current

V_CCRESET# Controlled Deep

Standby Current

Automatic Sleep Mode

Current ^5,

V_CCCE# Controlled Normal

Standby Current ²

V_CCRESET# Controlled

Normal Standby Current ²

16

2

4

mA

I_CC2

I_CC3

30

50

1

5

1

μA

I_CC4

I_CC5

I_CC6

I_CC7

RESET# = V_SS± 0.3 V

V_IH= V_CC± 0.3 V,

V_IL= V_SS± 0.3 V

μA

CE# = RESET# = V_IH

RESET# = V_IL

mA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.5

0.7 x V_CC

0.8

V_CC+ 0.3

V

Voltage for Electronic ID and

Temporary Sector Unprotect

V_ID

V_OL

V_CC= 3.3V

11.5

12.5

0.45

V

V_CC= V_CCMin,

Output Low Voltage

I

_OL= 4.0 mA

V_CC= V_CCMin,

I_OH= -2.0 mA

V_CC= V_CCMin,

V_OH1

V_OH2

0.85 x V_CC

Output High Voltage

V_CC- 0.4

2.3

V

I

_OH= -100 μA

V_LKO

Low V_CCLockout Voltage⁴

2.5

Notes:

1. The I_CCcurrent is listed is typically less than 2 mA/MHz with OE# at V_IH. Typical V_CCis 3.0 V.

2. All specifications are tested with V_CC= V_CCMax unless otherwise noted.

3. I_CCactive while the Automatic Erase or Automatic Program algorithm is in progress.

4. Not 100% tested.

5. Automatic sleep mode is enabled when addresses remain stable for t_ACC+ 30 ns (typical).

Rev. 1.2/May 01

25

HY29LV160

DC CHARACTERISTICS

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz.

Figure 11. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

3.6 V

10

8

2.7 V

6

4

2

0

1

2

3

4

5

6

Frequency in MHz

Note: T = 25 °C.

Figure 12. Typical I_CC1Current vs. Frequency

Rev. 1.2/May 01

26

HY29LV160

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Centerline is High Impedance State

(High Z)

TEST CONDITIONS

Table 12. Test Specifications

+ 3.3V

Test

Condition

Output Load

- 70 - 90

- 80 - 12

Unit

1 TTL Gate

100

2.7

KOhm

Output Load Capacitance (C_L)

Input Rise and Fall Times

Input Signal Low Level

30

pF

ns

V

5

DEVICE

UNDER

TEST

0.0

3.0

All diodes

are

Input Signal High Level

V

1N3064

or

equivalent

6.2

KOhm

Low Timing Measurement

Signal Level

C_L

1.5

V

High Timing Measurement

Signal Level

Note: Timing measurements are made at the reference

levels specified above regardless of where the illustrations

in the timing diagrams appear to indicate the measurement

is made

Figure 13. Test Setup

3.0 V

0.0 V

I

nput

1.5 V

Measurement Level

1.5 V

Output

Figure 14. Input Waveforms and Measurement Levels

Rev. 1.2/May 01

27

HY29LV160

AC CHARACTERISTICS

Read Operations

Parameter

Speed Option

Description

Test Setup

Unit

JEDEC

Std

- 70 - 80 - 90 - 12

t_AVAV

t_RCRead Cycle Time ¹

Min 70

80

90

120

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACCAddress to Output Delay

Max 70

80

90

120

t_ELQV

t_EHQZ

t_GLQV

t_GHQZ

t_CEChip Enable to Output Delay

t_DFChip Enable to Output High Z¹

t_OEOutput Enable to Output Delay

t_DFOutput Enable to Output High Z¹

OE# = V_ILMax 70

Max 25

80

25

30

25

90

30

35

30

120

30

ns

CE# = V_ILMax 30

Max 25

50

30

Read

Min

0

Output Enable

t_OEH

Toggle and

Data# Polling

Hold Time ¹

Min

10

ns

Output Hold Time from Addresses, CE#

or OE#, Whichever Occurs First

t_AXQX

t_OH

0

1

Notes:

1. Not 100% tested.

2. See Figure 13 and Table 12 for test conditions.

t_RC

Addresses

CE#

Addresses Stable

t_ACC

t_OE

OE#

t_OEH

t_DF

WE#

Outputs

RESET#

t_CE

t_OH

Output Valid

RY/BY#

0 V

Figure 15. Read Operation Timings

Rev. 1.2/May 01

28

HY29LV160

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

Speed Option

Description

Test Setup

Unit

JEDEC

Std

- 70 - 80 - 90 - 12

RESET# Pin Low (During Automatic

Algorithms) to Read or Write ¹

t_READY

Max

20

μs

ns

RESET# Pin Low (NOT During Automatic

Algorithms) to Read or Write ¹

t_READY

500

t_RPRESET# Pulse Width

Min

Max

Min

500

50

20

0

ns

μs

ns

t_RHRESET# High Time Before Read ¹

t_RPDRESET# Low to Standby Mode

t_RBRY/BY# Recovery Time

Notes:

1. Not 100% tested.

2. See Figure 13 and Table 12 for test conditions.

RY/BY#

0 V

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT During Automatic Algorithms

t_Ready

RY/BY#

CE#, OE#

RESET#

t_RB

t_RP

Reset Timings During Automatic Algorithms

Figure 16. RESET# Timings

Rev. 1.2/May 01

29

HY29LV160

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Option

Description

Unit

JEDEC

Std

- 70 - 80 - 90 - 12

t_ELFLCE# to BYTE# Switching Low

Max

5

ns

t_ELFHCE# to BYTE# Switching High

t_FLQZBYTE# Switching Low to Output High-Z

t_FHQVBYTE# Switching High to Output Active

Max 25

Min 70

25

80

30

90

30

120

CE#

OE#

BYTE#

switching

from word to

byte mode

t_ELFL

Data Output DQ[14:0]

Data Output DQ[7:0]

Address Input A-1

DQ[14:0]

Output DQ[15]

DQ[15]/A-1

t_FLQZ

BYTE#

switching

Data Output DQ[7:0]

Data Output DQ[14:0]

Data Output DQ[15]

DQ[14:0]

from byte to

word mode

Address Input A-1

DQ[15]/A-1

t_ELFH

t_FHQV

Figure 17. BYTE# Timings for Read Operations

CE#

Falling edge of the last WE# signal

WE#

t_SET(t_AS

)

BYTE#

t_HOLD(t_AH

)

Note: Refer to the Program/Erase Operations table for t_ASand t_AHspecifications.

Figure 18. BYTE# Timings for Write Operations

Rev. 1.2/May 01

30

HY29LV160

AC CHARACTERISTICS

Program and Erase Operations

Parameter

Speed Option

- 70 - 80 - 90 - 12

Description

Unit

JEDEC

t_AVAV

Std

t_WCWrite Cycle Time ¹

Min 70

Min

80

90

120

ns

t_AVWL

t_AS

Address Setup Time

0

t_WLAX

t_DVWH

t_WHDX

t_GHWL

t_ELWL

t_AHAddress Hold Time

t_DSData Setup Time

t_DHData Hold Time

Min 45

Min 35

Min

45

35

45

50

ns

0

ns

t_GHWLRead Recovery Time Before Write

t_CSCE# Setup Time

Min

ns

Min

ns

t_WHEH

t_WLWH

t_WHWL

t_CHCE# Hold Time

Min

ns

t_WPWrite Pulse Width

Min 35

Min

35

50

ns

t_WPHWrite Pulse Width High

30

9

ns

Typ

μs

Byte Mode

Word Mode

Byte Mode

Word Mode

Max

300

18

μs

t_WHWH1t_WHWH1Programming Operation ^{1, 2, 3}

Typ

μs

Max

500

18

μs

Typ

sec

Max

54

Chip Programming Operation ^{1, 2, 3, 5}

Typ

18

Max

54

Typ

0.25

5

t_WHWH2t_WHWH2Sector Erase Operation ^{1, 2, 4}

t_WHWH3t_WHWH3Chip Erase Operation ^{1, 2, 4}

Erase and Program Cycle Endurance ¹

Max

Typ

8

sec

Typ

Min

1,000,000

cycles

μs

100,000

t_VCSV_CCSetup Time ¹

50

0

t_RBRecovery Time from RY/BY#

t_BUSYWE# High to RY/BY# Delay

ns

90

ns

Notes:

1. Not 100% tested.

2. Typical program and erase times assume the following conditions: 25 °C, V_CC= 3.0 volts, 100,000 cycles. In addition,

programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-

tions of 90 °C, V_CC= 2.7 volts (3.0 volts for - 70 version), 100,000 cycles.

3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program

command. See Table 6 for further information on command sequences.

4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes

are programmed to 0x00 before erasure.

5. The typical chip programming time is considerably less than the maximum chip programming time listed since most

bytes/words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the

maximum byte/word program time specified is exceeded. See Write Operation Status section for additional information.

Rev. 1.2/May 01

31

HY29LV160

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_{W C}

t_AS

t_A

電子百科

產(chǎn)品導(dǎo)航

產(chǎn)品型號(hào)HY29LV160TT-12的Datasheet PDF文件預(yù)覽