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  • 北京元坤偉業(yè)科技有限公司

         該會(huì)員已使用本站17年以上

  • HY29F002
  • 數(shù)量-
  • 廠家-
  • 封裝-
  • 批號(hào)-
  • -
  • QQ:857273081QQ:857273081 復(fù)制
    QQ:1594462451QQ:1594462451 復(fù)制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • HY29F002TC-90圖
  • 深圳市恒達(dá)億科技有限公司

     該會(huì)員已使用本站12年以上
  • HY29F002TC-90 現(xiàn)貨庫存
  • 數(shù)量3000 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)25+ 
  • 原裝正品特價(jià)銷售
  • QQ:867789136QQ:867789136 復(fù)制
    QQ:1245773710QQ:1245773710 復(fù)制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • HY29F002TC-70圖
  • 深圳市芯脈實(shí)業(yè)有限公司

     該會(huì)員已使用本站11年以上
  • HY29F002TC-70 現(xiàn)貨庫存
  • 數(shù)量6980 
  • 廠家HYNIX 
  • 封裝PLCC32 
  • 批號(hào)22+ 
  • 新到現(xiàn)貨、一手貨源、當(dāng)天發(fā)貨、bom配單
  • QQ:2881512844QQ:2881512844 復(fù)制
  • 075584507705 QQ:2881512844
  • HY29F002TC-70圖
  • 深圳市宏世佳電子科技有限公司

     該會(huì)員已使用本站13年以上
  • HY29F002TC-70 現(xiàn)貨庫存
  • 數(shù)量3500 
  • 廠家HY 
  • 封裝PLCC 
  • 批號(hào)2023+ 
  • 全新原廠原裝產(chǎn)品、公司現(xiàn)貨銷售
  • QQ:2881894392QQ:2881894392 復(fù)制
    QQ:2881894393QQ:2881894393 復(fù)制
  • 0755- QQ:2881894392QQ:2881894393
  • HY29F002TC-90圖
  • 深圳市賽科世紀(jì)電子有限公司

     該會(huì)員已使用本站11年以上
  • HY29F002TC-90 現(xiàn)貨庫存
  • 數(shù)量63820 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)22+ 
  • 代理新到原裝現(xiàn)貨,特價(jià),13006691066
  • QQ:124766973QQ:124766973 復(fù)制
  • 13006691066 QQ:124766973
  • HY29F002TC-70圖
  • 首天國際(深圳)科技有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002TC-70
  • 數(shù)量128000 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)2024+ 
  • 百分百原裝正品,現(xiàn)貨庫存
  • QQ:528164397QQ:528164397 復(fù)制
    QQ:1318502189QQ:1318502189 復(fù)制
  • 0755-82807802 QQ:528164397QQ:1318502189
  • HY29F002TT圖
  • 北京中其偉業(yè)科技有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002TT
  • 數(shù)量4950 
  • 廠家 
  • 封裝TSOP 
  • 批號(hào)16+ 
  • 特價(jià),原裝正品,絕對(duì)公司現(xiàn)貨庫存,原裝特價(jià)!
  • QQ:2880824479QQ:2880824479 復(fù)制
  • 010-62104891 QQ:2880824479
  • HY29F002TC90圖
  • 北京首天國際有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002TC90
  • 數(shù)量247 
  • 廠家HYUNDAI 
  • 封裝PLCC 
  • 批號(hào)2024+ 
  • 百分百原裝正品,現(xiàn)貨庫存
  • QQ:528164397QQ:528164397 復(fù)制
    QQ:1318502189QQ:1318502189 復(fù)制
  • 010-62565447 QQ:528164397QQ:1318502189
  • HY29F002PC-70圖
  • 北京首天國際有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002PC-70
  • 數(shù)量7850 
  • 廠家HY 
  • 封裝SOP 
  • 批號(hào)2024+ 
  • 百分百原裝正品,現(xiàn)貨庫存
  • QQ:528164397QQ:528164397 復(fù)制
    QQ:1318502189QQ:1318502189 復(fù)制
  • 010-62565447 QQ:528164397QQ:1318502189
  • HY29F002TT-55圖
  • 北京齊天芯科技有限公司

     該會(huì)員已使用本站15年以上
  • HY29F002TT-55
  • 數(shù)量5000 
  • 廠家HY 
  • 封裝原廠封裝 
  • 批號(hào)2024+ 
  • 原裝正品,假一罰十
  • QQ:2880824479QQ:2880824479 復(fù)制
    QQ:1344056792QQ:1344056792 復(fù)制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • HY29F002圖
  • 北京中其偉業(yè)科技有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002
  • 數(shù)量2480 
  • 廠家HYUNDAI 
  • 封裝PLCC32 
  • 批號(hào)16+ 
  • 特價(jià),原裝正品,絕對(duì)公司現(xiàn)貨庫存,原裝特價(jià)!
  • QQ:2880824479QQ:2880824479 復(fù)制
  • 010-62104891 QQ:2880824479
  • HY29F002PC-70圖
  • 深圳市華斯頓電子科技有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002PC-70
  • 數(shù)量14772 
  • 廠家HYUNDAI 
  • 封裝TSOP 
  • 批號(hào)2023+ 
  • 絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨
  • QQ:1002316308QQ:1002316308 復(fù)制
    QQ:515102657QQ:515102657 復(fù)制
  • 深圳分公司0755-83777708“進(jìn)口原裝正品專供” QQ:1002316308QQ:515102657
  • HY29F002TC-00圖
  • 深圳市捷立輝科技有限公司

     該會(huì)員已使用本站10年以上
  • HY29F002TC-00
  • 數(shù)量89689 
  • 廠家HYUNDAI 
  • 封裝PLCC32 
  • 批號(hào)21+ 
  • 庫存現(xiàn)貨
  • QQ:1803576909QQ:1803576909 復(fù)制
  • -0755-82792948 QQ:1803576909
  • HY29F002TC-70圖
  • 深圳市得捷芯城科技有限公司

     該會(huì)員已使用本站11年以上
  • HY29F002TC-70
  • 數(shù)量3397 
  • 廠家HY 
  • 封裝NA/ 
  • 批號(hào)23+ 
  • 原裝現(xiàn)貨,當(dāng)天可交貨,原型號(hào)開票
  • QQ:3007977934QQ:3007977934 復(fù)制
    QQ:3007947087QQ:3007947087 復(fù)制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • HY29F002TC-90圖
  • 深圳市恒益昌科技有限公司

     該會(huì)員已使用本站6年以上
  • HY29F002TC-90
  • 數(shù)量3000 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)25+ 
  • 原裝正品長期供貨
  • QQ:3336148967QQ:3336148967 復(fù)制
    QQ:974337758QQ:974337758 復(fù)制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • HY29F002TC-90圖
  • 上海熠富電子科技有限公司

     該會(huì)員已使用本站15年以上
  • HY29F002TC-90
  • 數(shù)量5000 
  • 廠家HY 
  • 封裝N/A 
  • 批號(hào)2024 
  • 上海原裝現(xiàn)貨庫存,歡迎查詢!
  • QQ:2719079875QQ:2719079875 復(fù)制
    QQ:2300949663QQ:2300949663 復(fù)制
  • 15821228847 QQ:2719079875QQ:2300949663
  • HY29F002PC-70圖
  • 深圳市芯福林電子有限公司

     該會(huì)員已使用本站15年以上
  • HY29F002PC-70
  • 數(shù)量65000 
  • 廠家HYUNDAI 
  • 封裝TSOP 
  • 批號(hào)23+ 
  • 真實(shí)庫存全新原裝正品!代理此型號(hào)
  • QQ:2881495753QQ:2881495753 復(fù)制
  • 0755-23605827 QQ:2881495753
  • HY29F002TT-55圖
  • 首天國際(深圳)集團(tuán)有限公司

     該會(huì)員已使用本站17年以上
  • HY29F002TT-55
  • 數(shù)量5000 
  • 廠家HY 
  • 封裝原廠封裝 
  • 批號(hào)2024+ 
  • 百分百原裝正品,現(xiàn)貨庫存
  • QQ:528164397QQ:528164397 復(fù)制
    QQ:1318502189QQ:1318502189 復(fù)制
  • 0755-82807088 QQ:528164397QQ:1318502189
  • HY29F002TC-70圖
  • 深圳市芯脈實(shí)業(yè)有限公司

     該會(huì)員已使用本站11年以上
  • HY29F002TC-70
  • 數(shù)量6980 
  • 廠家HYNIX 
  • 封裝PLCC32 
  • 批號(hào)22+ 
  • 新到現(xiàn)貨、一手貨源、當(dāng)天發(fā)貨、bom配單
  • QQ:2881512844QQ:2881512844 復(fù)制
  • 075584507705 QQ:2881512844
  • HY29F002TC-70圖
  • 深圳市毅創(chuàng)騰電子科技有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002TC-70
  • 數(shù)量1651 
  • 廠家HYNIX 
  • 封裝PLCC32 
  • 批號(hào)22+ 
  • ★只做原裝★正品現(xiàn)貨★原盒原標(biāo)★
  • QQ:2355507168QQ:2355507168 復(fù)制
    QQ:2355507169QQ:2355507169 復(fù)制
  • 86-755-83219286 QQ:2355507168QQ:2355507169
  • HY29F002TC-90圖
  • 深圳市硅諾電子科技有限公司

     該會(huì)員已使用本站8年以上
  • HY29F002TC-90
  • 數(shù)量30542 
  • 廠家 
  • 封裝PLCC 
  • 批號(hào)17+ 
  • 原廠指定分銷商,有意請(qǐng)來電或QQ洽談
  • QQ:1091796029QQ:1091796029 復(fù)制
    QQ:916896414QQ:916896414 復(fù)制
  • 0755-82772151 QQ:1091796029QQ:916896414
  • HY29F002TT-55圖
  • 深圳市歐立現(xiàn)代科技有限公司

     該會(huì)員已使用本站12年以上
  • HY29F002TT-55
  • 數(shù)量6709 
  • 廠家HY 
  • 封裝TSOP32 
  • 批號(hào)24+ 
  • 全新原裝現(xiàn)貨,歡迎詢購!
  • QQ:1950791264QQ:1950791264 復(fù)制
    QQ:221698708QQ:221698708 復(fù)制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • HY29F002TC-90圖
  • 深圳市晶美隆科技有限公司

     該會(huì)員已使用本站14年以上
  • HY29F002TC-90
  • 數(shù)量13860 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)23+ 
  • 全新原裝正品現(xiàn)貨熱賣
  • QQ:2885348339QQ:2885348339 復(fù)制
    QQ:2885348317QQ:2885348317 復(fù)制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • HY29F002TC-90圖
  • 千層芯半導(dǎo)體(深圳)有限公司

     該會(huì)員已使用本站9年以上
  • HY29F002TC-90
  • 數(shù)量44300 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)2019+ 
  • 原裝進(jìn)口現(xiàn)貨假一罰百
  • QQ:2685694974QQ:2685694974 復(fù)制
    QQ:2593109009QQ:2593109009 復(fù)制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • HY29F002TC-70圖
  • 深圳市全源通電子有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002TC-70
  • 數(shù)量11698 
  • 廠家 
  • 封裝PLCC32 
  • 批號(hào)2010 
  • {優(yōu)勢(shì)}庫存,配套各式電子
  • QQ:2880072535QQ:2880072535 復(fù)制
  • 13430674577 QQ:2880072535
  • HY29F002TC-70圖
  • 深圳市晶美隆科技有限公司

     該會(huì)員已使用本站15年以上
  • HY29F002TC-70
  • 數(shù)量19800 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)24+ 
  • 假一罰十,原裝進(jìn)口正品現(xiàn)貨供應(yīng),價(jià)格優(yōu)勢(shì)。
  • QQ:198857245QQ:198857245 復(fù)制
  • 0755-82865294 QQ:198857245
  • HY29F002TC-90圖
  • 深圳市宏世佳電子科技有限公司

     該會(huì)員已使用本站13年以上
  • HY29F002TC-90
  • 數(shù)量3570 
  • 廠家HYUNDAI 
  • 封裝32PLCC 
  • 批號(hào)2023+ 
  • 全新原廠原裝產(chǎn)品、公司現(xiàn)貨銷售
  • QQ:2881894392QQ:2881894392 復(fù)制
    QQ:2881894393QQ:2881894393 復(fù)制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • HY29F002TC-45圖
  • 上海金慶電子技術(shù)有限公司

     該會(huì)員已使用本站15年以上
  • HY29F002TC-45
  • 數(shù)量191 
  • 廠家HYNIX 
  • 封裝 
  • 批號(hào)新 
  • 全新原裝 貨期兩周
  • QQ:1484215649QQ:1484215649 復(fù)制
    QQ:729272152QQ:729272152 復(fù)制
  • 021-51872561 QQ:1484215649QQ:729272152
  • HY29F002TT-90圖
  • 上海意淼電子科技有限公司

     該會(huì)員已使用本站14年以上
  • HY29F002TT-90
  • 數(shù)量20000 
  • 廠家HY 
  • 封裝TSOP32 
  • 批號(hào)23+ 
  • 原裝現(xiàn)貨熱賣!請(qǐng)聯(lián)系吳先生 13681678667
  • QQ:617677003QQ:617677003 復(fù)制
  • 15618836863 QQ:617677003
  • HY29F002TC-90圖
  • 深圳市昌和盛利電子有限公司

     該會(huì)員已使用本站11年以上
  • HY29F002TC-90
  • 數(shù)量7658 
  • 廠家【原裝正品專賣★價(jià)格最低】 
  • 封裝PLCC32 
  • 批號(hào)▊ NEW ▊ 
  • ◆★█【專注原裝正品現(xiàn)貨】★價(jià)格最低★!量大可定!歡迎惠顧!(長期高價(jià)回收全新原裝正品電子元器件)
  • QQ:1551106297QQ:1551106297 復(fù)制
    QQ:3059638860QQ:3059638860 復(fù)制
  • 0755-23125986 QQ:1551106297QQ:3059638860
  • HY29F002PC-70圖
  • 深圳市楷興電子科技有限公司

     該會(huì)員已使用本站7年以上
  • HY29F002PC-70
  • 數(shù)量10500 
  • 廠家HYUNDAI 
  • 封裝TSOP 
  • 批號(hào)21+ 
  • 原裝現(xiàn)貨庫存可出樣品
  • QQ:2881475151QQ:2881475151 復(fù)制
  • 0755-83016042 QQ:2881475151
  • HY29F002TC-70圖
  • 深圳市浩興林電子有限公司

     該會(huì)員已使用本站16年以上
  • HY29F002TC-70
  • 數(shù)量9500 
  • 廠家 
  • 封裝PLCC32 
  • 批號(hào)2017+ 
  • 誠信經(jīng)營,特價(jià)出售
  • QQ:382716594QQ:382716594 復(fù)制
    QQ:351622092QQ:351622092 復(fù)制
  • 0755-82532799 QQ:382716594QQ:351622092
  • HY29F002TC-45圖
  • 深圳市勵(lì)創(chuàng)源科技有限公司

     該會(huì)員已使用本站2年以上
  • HY29F002TC-45
  • 數(shù)量35600 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)21+ 
  • 誠信經(jīng)營,原裝現(xiàn)貨,假一賠十,歡迎咨詢15323859243
  • QQ:815442201QQ:815442201 復(fù)制
    QQ:483601579QQ:483601579 復(fù)制
  • -0755-82711370 QQ:815442201QQ:483601579
  • HY29F002TC-70圖
  • 深圳市匯滿鑫電子科技有限公司

     該會(huì)員已使用本站3年以上
  • HY29F002TC-70
  • 數(shù)量2021 
  • 廠家回收IC 
  • 封裝回收公司呆料 回收此型號(hào) 尋找代理渠道 
  • 批號(hào)
  • QQ:492609889QQ:492609889 復(fù)制
  • 0755-13828837567 QQ:492609889
  • HY29F002TC-90圖
  • 深圳市深美諾電子科技有限公司

     該會(huì)員已使用本站9年以上
  • HY29F002TC-90
  • 數(shù)量30 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)21+ 
  • 原裝現(xiàn)貨優(yōu)勢(shì)產(chǎn)品
  • QQ:945659508QQ:945659508 復(fù)制
  • 13751195054 QQ:945659508
  • HY29F002TC-90圖
  • 深圳市億智騰科技有限公司

     該會(huì)員已使用本站8年以上
  • HY29F002TC-90
  • 數(shù)量16680 
  • 廠家HYNIX 
  • 封裝PLCC 
  • 批號(hào)16+ 
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產(chǎn)品型號(hào)HY29F002的Datasheet PDF文件預(yù)覽

HY29F002T  
2 Megabit (256K x 8), 5 Volt-only, Flash Memory  
KEY FEATURES  
n 5 Volt Read, Program, and Erase  
n Sector Protection  
– Minimizes system-level power requirements  
n High Performance  
– Any combination of sectors may be  
locked to prevent program or erase  
operations within those sectors  
– Access times as fast as 45 ns  
n Low Power Consumption  
– 20 mA typical active read current  
– 30 mA typical program/erase current  
– 1 μA typical CMOS standby current  
n Compatible with JEDEC Standards  
– Package, pinout and command-set  
compatible with the single-supply Flash  
device standard  
– Provides superior inadvertent write  
protection  
n Sector Erase Architecture  
– Boot sector architecture with top boot  
block location  
n Temporary Sector Unprotect  
– Allows changes in locked sectors  
(requires high voltage on RESET# pin)  
n Internal Erase Algorithm  
– Automatically erases a sector, any  
combination of sectors, or the entire chip  
n Internal Programming Algorithm  
– Automatically programs and verifies data  
at a specified address  
n Fast Program and Erase Times  
– Byte programming time: 7 μs typical  
– Sector erase time: 1.0 sec typical  
– Chip erase time: 7 sec typical  
n Data# Polling and Toggle Status Bits  
– Provide software confirmation of  
completion of program or erase  
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte  
and three 64K byte sectors  
– A command can erase any combination of  
sectors  
operations  
– Supports full chip erase  
n Minimum 100,000 Program/Erase Cycles  
n Space Efficient Packaging  
n Erase Suspend/Resume  
– Temporarily suspends a sector erase  
operation to allow data to be read from, or  
programmed into, any sector not being  
erased  
– Available in industry-standard 32-pin  
TSOP and PLCC packages  
GENERAL DESCRIPTION  
LOGIC DIAGRAM  
The HY29F002T is an 2 Megabit, 5 volt-only  
CMOS Flash memory organized as 262,144  
(256K) bytes. The device is offered in industry-  
standard 32-pin TSOP and PLCC packages.  
18  
8
The HY29F002T can be programmed and erased  
in-system with a single 5-volt VCC supply. Inter-  
nally generated and regulated voltages are pro-  
vided for program and erase operations, so that  
the device does not require a high voltage power  
supply to perform those functions. The device can  
also be programmed in standard EPROM pro-  
grammers. Access times as fast as 55ns over the  
full operating voltage range of 5.0 volts ± 10% are  
offered for timing compatibility with the zero wait  
state requirements of high speed microprocessors.  
A 45ns version operating over 5.0 volts ± 5% is  
also available. To eliminate bus contention, the  
A[17:0]  
RESET#  
CE#  
DQ[7:0]  
OE#  
W E#  
Revision 4.1, May 2001  
HY29F002T  
HY29F002T has separate chip enable (CE#), write  
enable (WE#) and output enable (OE#) controls.  
the device has a Sector Protect function which  
hardware write protects selected sectors. The  
sector protect and unprotect features can be en-  
abled in a PROM programmer. Temporary Sec-  
tor Unprotect, which requires a high voltage, al-  
lows in-system erasure and code changes in pre-  
viously protected sectors.  
The device is compatible with the JEDEC single  
power-supply Flash command set standard. Com-  
mands are written to the command register using  
standard microprocessor write timings, from where  
they are routed to an internal state-machine that  
controls the erase and programming circuits.  
Device programming is performed a byte at a time  
by executing the four-cycle Program Command.  
This initiates an internal algorithm that automati-  
cally times the program pulse widths and verifies  
proper cell margin.  
Erase Suspend enables the user to put erase on  
hold for any period of time to read data from, or  
program data to, any sector that is not selected  
for erasure. True background erase can thus be  
achieved. The device is fully erased when shipped  
from the factory.  
The HY29F002Ts sector erase architecture allows  
any number of array sectors to be erased and re-  
programmed without affecting the data contents  
of other sectors. Device erasure is initiated by  
executing the Erase Command. This initiates an  
internal algorithm that automatically preprograms  
the array (if it is not already programmed) before  
executing the erase operation. During erase  
cycles, the device automatically times the erase  
pulse widths and verifies proper cell margin.  
Addresses and data needed for the programming  
and erase operations are internally latched during  
write cycles, and the host system can detect  
completion of a program or erase operation by  
reading the DQ[7] (Data# Polling) and DQ[6]  
(toggle) status bits. Reading data from the device  
is similar to reading from SRAM or EPROM de-  
vices. Hardware data protection measures include  
a low VCC detector that automatically inhibits write  
operations during power transitions.  
To protect data in the device from accidental or  
unauthorized attempts to program or erase the  
device while it is in the system (e.g., by a virus),  
The host can place the device into the standby  
mode. Power consumption is greatly reduced in  
this mode.  
BLOCK DIAGRAM  
DQ[7:0]  
STATE  
CONTROL  
ERASE VOLTAGE  
I/O BUFFERS  
DQ[7:0]  
GENERATOR AND  
COMMAND  
REGISTER  
SECTOR SWITCHES  
WE#  
CE#  
I/O CONTROL  
DATA LATCH  
OE#  
ELECTRONIC  
ID  
RESET#  
PROGRAM  
VOLTAGE  
GENERATOR  
Y-DECODER  
X-DECODER  
Y-GATING  
VSS  
2 MBIT  
FLASH  
MEMORY  
ARRAY  
VC C  
VC C DETECTOR  
TIMER  
A[17:0]  
(7 Sectors)  
Rev. 4.1/May 01  
2
HY29F002T  
PIN CONFIGURATIONS  
A[11]  
A[9]  
1
2
3
4
5
6
7
32  
31  
30  
29  
28  
27  
26  
OE#  
A[10]  
CE#  
A[8]  
A[13]  
A[14]  
A[17]  
WE#  
DQ[7]  
DQ[6]  
DQ[5]  
DQ[4]  
VC C  
RESET#  
8
9
25  
24  
DQ[3]  
VSS  
TSOP32  
A[16]  
A[15]  
10  
11  
23  
22  
DQ[2]  
DQ[1]  
A[12]  
A[7]  
12  
13  
21  
20  
DQ[0]  
A[0]  
A[6]  
A[5]  
A[4]  
14  
15  
16  
19  
18  
17  
A[1]  
A[2]  
A[3]  
4
3
2
1 32 31 30  
A[7]  
A[6]  
5
6
29  
28  
27  
26  
25  
24  
23  
22  
21  
A[14]  
A[13]  
A[8]  
A[5]  
7
A[4]  
8
A[9]  
A[3]  
9
A[11]  
OE#  
A[10]  
CE#  
PLCC32  
A[2]  
10  
11  
12  
13  
A[1]  
A[0]  
DQ[0]  
DQ[7]  
14 15 16 17 18 19 20  
CONVENTIONS  
Whenever a signal is separated into numbered  
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of  
bits may also be shown collectively, e.g., as  
DQ[7:0].  
Unless otherwise noted, a positive logic (active  
High) convention is assumed throughout this docu-  
ment, whereby the presence at a pin of a higher,  
more positive voltage (nominally 5VDC) causes  
assertion of the signal. A #symbol following the  
signal name, e.g., RESET#, indicates that the sig-  
nal is asserted in a Low state (nominally 0 volts).  
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .  
. . , E, F) indicates a number expressed in hexa-  
decimal notation. The designation 0bXXXX indi-  
cates a number expressed in binary notation (X =  
0, 1).  
Rev. 4.1/May 01  
3
HY29F002T  
SIGNAL DESCRIPTIONS  
Name  
Type  
Description  
Address, active High. These eighteen inputs select one of 262,144 (256K)  
bytes within the array for read or write operations. A[17] is the MSB and A[0] is  
the LSB.  
A[17:0]  
Inputs  
Inputs/Outputs Data Bus, active High. These pins provide an 8-bit data path for read and  
DQ[7:0]  
CE#  
Tri-state  
write operations.  
Chip Enable, active Low. This input must be asserted to read data from or  
write data to the HY29F002T. When High, the data bus is tri-stated and the  
device is placed in the Standby mode.  
Input  
Output Enable, active Low. This input must be asserted for read operations  
and negated for write operations. When High, data outputs from the device are  
disabled and the data bus pins are placed in the high impedance state.  
OE#  
WE#  
Input  
Input  
Write Enable, active Low. Controls writing of commands or command  
sequences in order to program data or perform other operations. A write  
operation takes place when WE# is asserted while CE# is Low and OE# is High.  
Hardware Reset, active Low. Provides a hardware method of resetting the  
HY29F002T to the read array state. When the device is reset, it immediately  
terminates anyoperation in progress. The data bus is tri-stated and all read/write  
commands are ignored while the input is asserted. While RESET# is asserted,  
the device will be in the Standby mode.  
RESET#  
Input  
5-volt (nominal) power supply.  
Power and signal ground.  
VCC  
VSS  
--  
--  
MEMORY ARRAY ORGANIZATION  
The 256 Kbyte Flash memory array is organized  
into seven blocks called sectors (S0, S1, . . . ,  
S6). A sector is the smallest unit that can be  
erased and which can be protected to prevent  
accidental or unauthorized erasure. See the Bus  
Operationsand Command Definitionssections  
of this document for additional information on these  
functions.  
In the HY29F002T, four of the sectors, which com-  
prise the boot block, vary in size from 8 to 32  
Kbytes, while the remaining three sectors are  
uniformly sized at 64 Kbytes. In this device, the  
boot block is located at the top of the address  
range.  
Table 1 defines the sector addresses and corre-  
sponding address ranges for the HY29F002T.  
Table 1. HY29F002T Memory Array Organization  
Sector Address  
Size  
Sector  
Address Range  
(Kbytes)  
A[17]  
A[16]  
A[15]  
A[14]  
A[13]  
S0  
S1  
S2  
S3  
S4  
S5  
S6  
64  
64  
64  
32  
8
0
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
0
1
1
1
X
X
X
X
0
X
X
X
X
0
0x00000 - 0x0FFFF  
0x10000 - 0x1FFFF  
0x20000 - 0x2FFFF  
0x30000 - 0x37FFF  
0x38000 - 0x39FFF  
0x3A000 - 0x3BFFF  
0x3C000 - 0x3FFFF  
8
0
1
16  
1
X
Rev. 4.1/May 01  
4
HY29F002T  
Table 2. HY29F002T Normal Bus Operations1  
Operation  
CE#  
OE#  
L
WE#  
H
RESET#  
A[17:0]  
DQ[7:0]  
Read  
Write  
L
H
AIN  
AIN  
X
DOUT  
DIN  
L
H
L
H
Output Disable  
L
H
H
H
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
CE# TTL Standby  
H
X
X
H
VCC ± 0.5V  
L
X
CE# CMOS Standby  
Hardware Reset (TTL Standby)  
Hardware Reset (CMOS Standby)  
Notes:  
V
CC ± 0.5V  
X
X
X
X
X
X
X
X
X
X
VSS ± 0.5V  
X
1. L = VIL, H = VIH, X = Dont Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.  
BUS OPERATIONS  
data from or program data into any sector of  
memory that is not marked for erasure. If the host  
attempts to read from an address within an erase-  
suspended sector, or while the device is perform-  
ing an erase or byte program operation, the de-  
vice outputs status data instead of array data. After  
completing a programming operation in the Erase  
Suspend mode, the system may once again read  
array data with the same exceptions noted above.  
After completing an internal program or internal  
erase algorithm, the HY29F002T automatically re-  
turns to the read array data mode.  
Device bus operations are initiated through the  
internal command register, which consists of sets  
of latches that store the commands, along with  
the address and data information, if any, needed  
to execute the specific command. The command  
register itself does not occupy any addressable  
memory location. The contents of the command  
register serve as inputs to an internal state ma-  
chine whose outputs control the operation of the  
device. Table 2 lists the normal bus operations,  
the inputs and control levels they require, and the  
resulting outputs. Certain bus operations require  
a high voltage on one or more device pins. Those  
are described in Table 3.  
The host must issue a hardware reset or the soft-  
ware reset command (see Command Definitions)  
to return a sector to the read array data mode if  
DQ[5] goes high during a program or erase cycle,  
or to return the device to the read array data mode  
while it is in the Electronic ID mode.  
Read Operation  
Data is read from the HY29F002T by using stan-  
dard microprocessor read cycles while placing the  
address of the byte to be read on the devices  
address inputs, A[17:0]. As shown in Table 2, the  
host system must drive the CE# and OE# inputs  
Low and drive WE# High for a valid read opera-  
tion to take place. The device outputs the speci-  
fied array data on DQ[7:0].  
Write Operation  
Certain operations, including programming data  
and erasing sectors of memory, require the host  
to write a command or command sequence to the  
HY29F002T. Writes to the device are performed  
by placing the byte address on the devices ad-  
dress inputs while the data to be written is input  
on DQ[7:0]. The host system must drive the CE#  
and WE# pins Low and drive OE# High for a valid  
write operation to take place. All addresses are  
latched on the falling edge of WE# or CE#, which-  
ever happens later. All data is latched on the ris-  
ing edge of WE# or CE#, whichever happens first.  
The HY29F002T is automatically set for reading  
array data after device power-up and after a hard-  
ware reset to ensure that no spurious alteration of  
the memory content occurs during the power tran-  
sition. No command is necessary in this mode to  
obtain array data, and the device remains enabled  
for read accesses until the command register con-  
tents are altered.  
This device features an Erase Suspend mode.  
While in this mode, the host may read the array  
Rev. 4.1/May 01  
5
HY29F002T  
Table 3. HY29F002T Bus Operations Requiring High Voltage 1, 2  
Operation 3  
CE# OE# WE# RESET# A[17:13] A[9] A[6] A[1] A[0] DQ[7:0]  
Sector Protect  
L
VID  
VID  
X
X
H
H
SA 4  
VID  
VID  
X
X
X
X
X
X
X
X
Sector Unprotect  
VID  
X
Temporary Sector  
Unprotect  
X
X
X
VID  
X
X
X
X
X
X
Manufacturer Code  
Device Code  
L
L
L
L
H
H
H
H
X
X
VID  
VID  
L
L
L
L
L
0xAD  
0xB0  
0x00  
H
Sector  
Unprotected  
Protected  
Protection  
Verification  
L
L
H
H
SA 4  
VID  
L
H
L
0x01  
Notes:  
1. L = VIL, H = VIH, X = Dont Care. See DC Characteristics for voltage levels.  
2. Address bits not specified are Dont Care.  
3. See text for additional information.  
4. SA = sector address. See Table 1.  
The Device Commandssection of this document  
provides details on the specific device commands  
implemented in the HY29F002T.  
The device requires standard access time (tCE) for  
read access when the device is in either of the  
standby modes, before it is ready to read data. If  
the device is deselected during erasure or pro-  
gramming, it continues to draw active current until  
the operation is completed.  
Output Disable Operation  
When the OE# input is at VIH, output data from the  
device is disabled and the data bus pins are placed  
in the high impedance state.  
Hardware Reset Operation  
The RESET# pin provides a hardware method of  
resetting the device to reading array data. When  
the RESET# pin is driven Low for the minimum  
specified period, the device immediately termi-  
nates any operation in progress, tri-states the data  
bus pins, and ignores all read/write commands for  
the duration of the RESET# pulse. The device also  
resets the internal state machine to reading array  
data. If an operation was interrupted by the as-  
sertion of RESET#, it should be reinitiated once  
the device is ready to accept another command  
sequence to ensure data integrity.  
Standby Operation  
When the system is not reading from or writing to  
the HY29F002T, it can place the device in the  
Standby mode. In this mode, current consump-  
tion is greatly reduced, and the data bus outputs  
are placed in the high impedance state, indepen-  
dent of the OE# input. The Standby mode can  
invoked using two methods.  
The device enters the CE# CMOS Standby mode  
if the CE# and RESET# pins are both held at VCC  
± 0.5V. Note that this is a more restricted voltage  
range than VIH. If both CE# and RESET# are held  
High, but not within VCC ± 0.5V, the device will be  
in the CE# TTL Standby mode, but the standby  
current will be greater.  
Current is reduced for the duration of the RESET#  
pulse as described in the Standby Operation sec-  
tion above.  
If RESET# is asserted during a program or erase  
operation, the internal reset operation is completed  
within a time of tREADY (during Automatic Algo-  
rithms). The system can perform a read or write  
operation after waiting for a minimum of tREADY or  
until tRH after the RESET# pin returns High, which-  
ever is longer. If RESET# is asserted when a pro-  
gram or erase operation is not executing, the re-  
The device enters the RESET# CMOS Standby  
mode when the RESET# pin is held at VSS ± 0.5V.  
If RESET# is held Low but not within VSS ± 0.5V,  
the HY29F002T will be in the RESET# TTL  
Standby mode, but the standby current will be  
greater. See Hardware Reset Operation section  
for additional information on the reset operation.  
Rev. 4.1/May 01  
6
HY29F002T  
set operation is completed within a time of tRP. In  
this case, the host can perform a read or write  
operation tRH after the RESET# pin returns High.  
unprotected sectors must first be protected prior  
to the first unprotect write cycle.  
Sectors can also be temporarily unprotected as  
The RESET# pin may be tied to the system reset  
signal. Thus, a system reset would also reset the  
device, enabling the system to read the boot-up  
firmware from the Flash memory.  
described in the next section.  
Temporary Sector Unprotect Operation  
This feature allows temporary unprotection of pre-  
viously protected sectors to allow changing the  
data in-system. Temporary Sector Unprotect  
mode is activated by setting the RESET# pin to  
VID. While in this mode, formerly protected sec-  
tors can be programmed or erased by invoking  
the appropriate commands (see Device Com-  
mands section). Once VID is removed from RE-  
SET#, all the previously protected sectors are pro-  
tected again. Figure 3 illustrates the algorithm.  
Sector Protect/Unprotect Operations  
Hardware sector protection can be invoked to dis-  
able program and erase operations in any single  
sector or combination of sectors. This function is  
typically used to protect data in the device from  
unauthorized or accidental attempts to program  
or erase the device while it is in the system (e.g.,  
by a virus) and is implemented using program-  
ming equipment. Sector unprotection re-enables  
the program and erase operations in previously  
protected sectors.  
Electronic ID Mode Operation  
The Electronic ID mode provides manufacturer and  
device identification and sector protection verifi-  
cation through identifier codes output on DQ[7:0].  
This mode is intended primarily for programming  
equipment to automatically match a device to be  
programmed with its corresponding programming  
algorithm. The Electronic ID information can also  
be obtained by the host through a command se-  
quence, as described in the Device Commands  
section.  
Table 1 identifies the seven sector in the top and  
bottom boot block versions of the HY29F002T and  
the address ranges that each covers. The device  
is shipped with all sectors unprotected.  
The sector protect/unprotect operations require a  
high voltage (VID) on address pin A[9] and the CE#  
and/or OE# control pins, as detailed in Table 3.  
When implementing these operations, note that  
V
CC must be applied to the device before applying  
VID, and that VID should be removed before remov-  
ing VCC from the device.  
Operation in the Electronic ID mode requires VID  
on address pin A[9], with additional requirements  
for obtaining specific data items as listed in Table  
2:  
The flow chart in Figure 1 illustrates the proce-  
dure for protecting sectors, and timing specifica-  
tions and waveforms are shown in the specifica-  
tions section of this document. Verification of pro-  
tection is accomplished as described in the Elec-  
tronic ID Mode section and shown in the flow chart.  
n A read cycle at address 0xXXX00 retrieves the  
manufacturer code (Hynix = 0xAD).  
n A read cycle at address 0xXXX01 returns the  
device code (HY29F002T = 0xB0).  
The procedure for sector unprotection is illustrated  
in the flow chart in Figure 2, and timing specifica-  
tions and waveforms are given at the end of this  
document. Note that to unprotect any sector, all  
n A read cycle containing a sector address (Table  
1) in A[17:13] and the address 0x02 in A[7:0]  
returns 0x01 if that sector is protected, or 0x00  
if it is unprotected.  
Rev. 4.1/May 01  
7
HY29F002T  
Wait tWPP1  
WE# = V IH  
START  
APPLY V  
CC  
A[9] = V ID  
A[17:13] = Sector to Protect  
OE# = CE# = V  
A[6] = A[0] = V  
Set TRYCNT = 1  
IL  
Increment TRYCNT  
IL  
A[1] = V IH  
Read Data  
NO  
TRYCNT = 25?  
YES  
Set A[9] = OE# = V  
ID  
NO  
Data = 0x01?  
YES  
Set Address:  
A[17:13] = Sector to Protect  
CE# = V IL  
RESET# = V  
IH  
Remove V  
from A[9]  
ID  
NO  
Protect Another  
Sector?  
WE# = V IL  
SECTOR PROTECT  
COMPLETE  
DEVICE FAILURE  
YES  
Figure 1. Sector Protect Procedure  
Rev. 4.1/May 01  
8
HY29F002T  
START  
NOTE: All sectors must be  
previously protected.  
Increment TRYCNT  
Set Sector Address:  
A[17:13] = Sector NSEC  
A[0] = A[6] = V  
APPLY V  
IL  
CC  
A[1] = V IH  
Set: TRYCNT = 1  
Read Data  
NO  
Set: NSEC = 0  
YES  
NO  
Data = 0x00?  
TRYCNT = 1000?  
Set: A[9] = CE# = OE# = V  
ID  
YES  
Set: RESET# = V  
IH  
YES  
WE# = V IL  
Wait t WPP2  
WE# = V IH  
Set:  
NSEC = 6?  
Remove V  
from A[9]  
ID  
NO  
NSEC = NSEC + 1  
SECTOR UNPROTECT  
COMPLETE  
DEVICE FAILURE  
A[9] = V  
ID  
OE# = CE# = V  
IL  
Figure 2. Sector Unprotect Procedure  
DEVICE COMMANDS  
START  
Device operations are initiated by writing desig-  
nated address and data command sequences into  
the device. A command sequence is composed  
of one, two or three of the following sub-segments:  
an unlock cycle, a command cycle and a data  
cycle. Table 4 summarizes the composition of the  
valid command sequences implemented in the  
HY29F002T, and these sequences are fully de-  
scribed in Table 5 and in the sections that follow.  
RESET# = VID  
(All protected sectors  
become unprotected)  
Perform Program or Erase  
Operations  
Writing incorrect address and data values or writ-  
ing them in the improper sequence resets the  
HY29F002T to the Read mode.  
RESET# = VIH  
(All previously protected  
sectors return to  
protected state)  
Read/Reset 1, 2 Commands  
TEMPORARY SECTOR  
UNPROTECT COMPLETE  
The HY29F002T automatically enters the Read  
mode after device power-up, after the RESET#  
input is asserted and upon the completion of cer-  
tain commands. Read/Reset commands are not  
required to retrieve data in these cases.  
Figure 3. Temporary Sector Unprotect  
Rev. 4.1/May 01  
9
HY29F002T  
Table 4. Composition of Command Sequences  
n In a Program command sequence, the Read/  
Reset command may be written between the  
sequence cycles before programming actually  
begins. This aborts the command and resets  
the device to the Read mode, or to the Erase  
Suspend mode if the Program command se-  
quence is written while the device is in the  
Erase Suspend mode. Once programming  
begins, however, the device ignores Read/Re-  
set commands until the operation is complete.  
Number of Bus Cycles  
Command  
Sequence  
Unlock Command  
Data  
Read/Reset 1  
Read/Reset 2  
Byte Program  
Chip Erase  
0
2
2
4
4
0
0
2
1
1
1
1
1
1
1
1
Note 1  
Note 1  
1
1
Sector Erase  
Erase Suspend  
Erase Resume  
Electronic ID  
1 (Note 2)  
n The Read/Reset command may be written be-  
tween the cycles in an Electronic ID command  
sequence to abort that command. As described  
above, once in the Electronic ID mode, the  
Read/ Reset command must be written to re-  
turn to the Read mode.  
0
0
Note 3  
Notes:  
1. Any number of Flash array read cycles are permitted.  
2. Additional data cycles may follow. See text.  
3. Any number of Electronic ID read cycles are permitted.  
Byte Program Command  
A Read/Reset command must be issued in order  
to read array data in the following cases:  
The host processor programs the device a byte at  
a time by issuing the Program command sequence  
shown in Table 5. The sequence begins by writ-  
ing two unlock cycles, followed by the Program  
setup command and, lastly, a data cycle specify-  
ing the program address and data. This initiates  
the Automatic Programming algorithm, which pro-  
vides internally generated program pulses and  
verifies the programmed cell margin. The host is  
not required to provide further controls or timings  
during this operation. When the Automatic Pro-  
gramming algorithm is complete, the device re-  
turns to the Read mode. Several methods are  
provided to allow the host to determine the status  
of the programming operation, as described in the  
Write Operation Status section.  
n If the device is in the Electronic ID mode, a  
Read/ Reset command must be written to re-  
turn to the Read mode. If the device was in the  
Erase Suspend mode when the device entered  
the Electronic ID mode, writing the Read/Re-  
set command returns the device to the Erase  
Suspend mode.  
Note: When in the Electronic ID bus operation mode,  
the device returns to the Read mode when VID is re-  
moved from the A[9] pin. The Read/Reset command is  
not required in this case.  
n If DQ[5] (Exceeded Time Limit) goes High dur-  
ing a program or erase operation, writing the  
reset command returns the sectors to the Read  
mode (or to the Erase Suspend mode if the  
device was in Erase Suspend).  
Commands written to the device during execution  
of the Automatic Programming algorithm are ig-  
nored. Note that a hardware reset immediately  
terminates the programming operation. To en-  
sure data integrity, the aborted program command  
sequence should be reinitiated once the reset  
operation is complete.  
The Read/Reset command may also be used to  
abort certain command sequences:  
n In a Sector Erase or Chip Erase command se-  
quence, the Read/Reset command may be  
written at any time before erasing actually be-  
gins, including, for the Sector Erase command,  
between the cycles that specify the sectors to  
be erased (see Sector Erase command de-  
scription). This aborts the command and re-  
sets the device to the Read mode. Once era-  
sure begins, however, the device ignores Read/  
Reset commands until the operation is com-  
plete.  
Programming is allowed in any sequence. Only  
erase operations can convert a stored 0to a 1.  
Thus, a bit cannot be programmed from a 0back  
to a 1. Attempting to do so will set DQ[5] to 1,  
and the Data# Polling algorithm will indicate that  
the operation was not successful. A Read/Reset  
command or a hardware reset is required to exit  
Rev. 4.1/May 01  
10  
HY29F002T  
Rev. 4.1/May 01  
11  
HY29F002T  
START  
START  
Issue PROGRAM  
Command Sequence:  
Last cycle contains  
Issue CHIP ERASE  
Command Sequence  
program Address/Data  
Check Erase Status  
(See Write Operation Status  
Section)  
Check Programming Status  
(See Write Operation Status  
Section)  
DQ[5] Error Exit  
DQ[5] Error Exit  
Normal Exit  
Normal Exit  
GO TO  
ERROR RECOVERY  
CHIP ERASE COMPLETE  
NO  
Last Word/Byte  
Done?  
Figure 5. Chip Erase Procedure  
YES  
mine the status of the erase operation, as de-  
scribed in the Write Operation Status section.  
PROGRAMMING  
COMPLETE  
GO TO  
ERROR RECOVERY  
Figure 5 illustrates the Chip Erase procedure.  
Figure 4. Programming Procedure  
this state, and a succeeding read will show that  
Sector Erase Command  
the data is still 0.  
The Sector Erase command sequence consists  
of two unlock cycles, followed by the erase com-  
mand, two additional unlock cycles and then the  
sector erase data cycle, which specifies which  
sector is to be erased. As described later in this  
section, multiple sectors can be specified for era-  
sure with a single command sequence. During  
sector erase, all specified sectors are erased se-  
quentially. The data in sectors not specified for  
erasure, as well as the data in any protected sec-  
tors specified for erasure, is not affected by the  
sector erase operation.  
Figure 4 illustrates the procedure for the Program  
operation.  
Chip Erase Command  
The Chip Erase command sequence consists of  
two unlock cycles, followed by the erase command,  
two additional unlock cycles and then the chip erase  
data cycle. During chip erase, all sectors of the  
device are erased except protected sectors. The  
command sequence starts the Automatic Erase al-  
gorithm, which preprograms and verifies the entire  
memory, except for protected sectors, for an all zero  
data pattern prior to electrical erase. The device  
then provides the required number of internally  
generated erase pulses and verifies cell erasure  
within the proper cell margins. The host system is  
not required to provide any controls or timings dur-  
ing these operations.  
The Sector Erase command sequence starts the  
Automatic Erase algorithm, which preprograms  
and verifies the specified unprotected sectors for  
an all zero data pattern prior to electrical erase.  
The device then provides the required number of  
internally generated erase pulses and verifies cell  
erasure within the proper cell margins. The host  
system is not required to provide any controls or  
timings during these operations.  
Commands written to the device during execution  
of the Automatic Erase algorithm are ignored. Note  
that a hardware reset immediately terminates the  
erase operation. To ensure data integrity, the  
aborted chip erase command sequence should be  
reissued once the reset operation is complete.  
After the sector erase data cycle (the sixth bus  
cycle) of the command sequence is issued, a sec-  
tor erase time-out of 50 μs (minimum), measured  
from the rising edge of the final WE# pulse in that  
bus cycle, begins. During this time, an additional  
sector erase data cycle, specifying the sector ad-  
dress of another sector to be erased, may be writ-  
ten into an internal sector erase buffer. This buffer  
When the Automatic Erase algorithm is finished,  
the device returns to the Read mode. Several  
methods are provided to allow the host to deter-  
Rev. 4.1/May 01  
12  
HY29F002T  
may be loaded in any sequence, and the number  
of sectors specified may be from one sector to all  
sectors. The only restriction is that the time be-  
tween these additional data cycles must be less  
than 50 μs, otherwise erasure may begin before  
the last data cycle is accepted. To ensure that all  
data cycles are accepted, it is recommended that  
host processor interrupts be disabled during the  
time that the additional cycles are being issued  
and then be re-enabled afterwards.  
nores the command for the selected sectors that  
are protected.  
The system can monitor DQ[3] to determine if the  
50 μs sector erase time-out has expired, as de-  
scribed in the Write Operation Status section. If  
the time between additional sector erase data  
cycles can be insured to be less than the time-  
out, the system need not monitor DQ[3].  
Any command other than Sector Erase or Erase  
Suspend during the time-out period resets the  
device to reading array data. The system must  
then rewrite the command sequence, including any  
additional sector erase data cycles. Once the  
sector erase operation itself has begun, only the  
Erase Suspend command is valid. All other com-  
mands are ignored.  
Note: The device is capable of accepting three ways  
of invoking Erase Commands for additional sectors  
during the time-out window. The preferred method,  
described above, is the sector erase data cycle after  
the initial six bus cycle command sequence. How-  
ever, the device also accepts the following methods  
of specifying additional sectors during the sector  
erase time-out:  
n Repeat the entire six-cycle command sequence, speci-  
fying the additional sector in the sixth cycle.  
n Repeat the last three cycles of the six-cycle command  
sequence, specifying the additional sector in the third  
cycle.  
As for the Chip Erase command, note that a hard-  
ware reset immediately terminates the erase op-  
eration. To ensure data integrity, the aborted Sec-  
tor Erase command sequence should be reissued  
once the reset operation is complete.  
If all sectors scheduled for erasing are within pro-  
tected sectors, the device returns to reading ar-  
ray data after approximately 100 μs. If at least  
one selected sector is not protected, the erase  
operation erases the unprotected sectors, and ig-  
When the Automatic Erase algorithm terminates,  
the device returns to the Read mode. Several  
methods are provided to allow the host to deter-  
mine the status of the erase operation, as de-  
scribed in the Write Operation Status section.  
START  
Check Erase Status  
DQ[5] Error Exit  
(See Write Operation Status  
Section)  
Normal Exit  
Write First Five Cycles of  
SECTOR ERASE  
Command Sequence  
GO TO  
ERASE COMPLETE  
ERROR RECOVERY  
Setup First (or Next) Sector  
Address for Erase Operation  
Write Last Cycle (SA/0x30)  
of SECTOR ERASE  
Command Sequence  
Sectors which require erasure  
but which were not specified in  
this erase cycle must be erased  
later using a new command  
sequence  
NO  
Sector Erase  
Time-out (DQ[3])  
Expired?  
Erase An  
Additional Sector?  
YES  
YES  
NO  
Figure 6. Sector Erase Procedure  
Rev. 4.1/May 01  
13  
HY29F002T  
Figure 6 illustrates the Sector Erase procedure.  
Suspend command can be written after the de-  
vice has resumed erasing.  
Erase Suspend/Erase Resume Commands  
The host may also write the Electronic ID com-  
mand sequence when the device is in the Erase  
Suspend mode. The device allows reading Elec-  
tronic ID codes even if the addresses used for the  
ID read cycles are within erasing sectors, since  
the codes are not stored in the memory array.  
When the device exits the Electronic ID mode, the  
device reverts to the Erase Suspend mode, and  
is ready for another valid operation. See Electronic  
ID section for more information.  
The Erase Suspend command allows the system  
to interrupt a sector erase operation to read data  
from, or program data in, any sector not being  
erased. The command causes the erase opera-  
tion to be suspended in all sectors selected for  
erasure. This command is valid only during the  
sector erase operation, including during the 50 μs  
time-out period at the end of the initial command  
sequence and any subsequent sector erase data  
cycles, and is ignored if it is issued during chip  
erase or programming operations.  
Electronic ID Command  
The HY29F002T requires a maximum of 20 μs to  
suspend the erase operation if the Erase Suspend  
command is issued during active sector erasure.  
However, if the command is written during the time-  
out, the time-out is terminated and the erase op-  
eration is suspended immediately. Any subse-  
quent attempts to specify additional sectors for  
erasure by writing the sector erase data cycle (SA/  
0x30) will be interpreted as the Erase Resume  
command (XXX/0x30), which will cause the Auto-  
matic Erase algorithm to begin its operation. Note  
that any other command during the time-out will  
reset the device to the Read mode.  
The Electronic ID operation intended for use in  
programming equipment has been described pre-  
viously. The host processor can also be obtain  
the same data by using the Electronic ID com-  
mand sequence shown in Table 5. This method  
does not require VID on any pin. The Electronic ID  
command sequence may be invoked while the  
device is in the Read mode or the Erase Suspend  
mode, but is invalid while the device is actively  
programming or erasing.  
The Electronic ID command sequence is initiated  
by writing two unlock cycles, followed by the Elec-  
tronic ID command. The device then enters the  
Electronic ID mode, and:  
Once the erase operation has been suspended,  
the system can read array data from or program  
data to any sector not selected for erasure. Nor-  
mal read and write timings and command defini-  
tions apply. Reading at any address within erase-  
suspended sectors produces status data on  
DQ[7:0]. The host can use DQ[7], or DQ[6] and  
DQ[2] together, to determine if a sector is actively  
erasing or is erase-suspended. See Write Op-  
eration Statusfor information on these status bits.  
n A read cycle at address 0xXXX00 retrieves the  
manufacturer code (Hynix = 0xAD).  
n A read cycle at address 0xXXX01 returns the  
device code (0xB0).  
n A read cycle containing a sector address in  
A[17:13] and the address 0x02 in A[7:0] returns  
0x01 if that sector is protected, or 0x00 if it is  
unprotected.  
After an erase-suspended program operation is  
complete, the host can initiate another program-  
ming operation (or read operation) within non-sus-  
pended sectors. The host can determine the sta-  
tus of a program operation during the erase-sus-  
pended state just as in the standard programming  
operation.  
The host system may read at any address any  
number of times, without initiating another com-  
mand sequence. Thus, for example, the host may  
determine the protection status for all sectors by  
doing successive reads at address 0x02 while  
changing the sector address in A[17:13] for each  
cycle.  
The system must write the Erase Resume com-  
mand to exit the Erase Suspend mode and con-  
tinue the sector erase operation. Further writes of  
the Resume command are ignored. Another Erase  
The system must write the Reset command to exit  
the Electronic ID mode and return to the Read  
mode, or to the Erase Suspend mode if the de-  
vice was in that mode when the command se-  
quence was issued.  
Rev. 4.1/May 01  
14  
HY29F002T  
Table 6. Write and Erase Operation Status Summary  
1
1
Mode  
Operation  
Programming in progress  
Programming completed  
Erase in progress  
DQ[7]  
DQ[6]  
Toggle  
Data 4  
DQ[5]  
0/1 2  
Data  
0/1 2  
Data  
0
DQ[3]  
N/A  
DQ[2]  
DQ[7]#  
Data  
0
N/A  
Data  
1 3  
Data  
Normal  
Toggle  
Data 4  
Toggle  
Data 4  
Toggle  
Data  
Erase completed  
1
Data  
N/A  
Read within erase suspended sector  
Read within non-erase suspended sector  
Programming in progress 5  
Programming completed 5  
1
No toggle  
Data  
Data  
DQ[7]#  
Data  
Data  
0/1 2  
Data  
Data  
N/A  
Erase  
Suspend  
Toggle  
Data 4  
N/A  
Data  
Data  
Notes:  
1. A valid address is required when reading status information. See text for additional information.  
2. DQ[5] status switches to a 1when a program or erase operation exceeds the maximum timing limit.  
3. A 1during sector erase indicates that the 50 μs timeout has expired and active erasure is in progress. DQ[3] is not  
applicable to the chip erase operation.  
4. Equivalent to No Togglebecause data is obtained in this state.  
5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).  
WRITE OPERATION STATUS  
an erase operation, Data# Polling produces a 0”  
on DQ[7]. When the erase operation is complete,  
or if the device enters the Erase Suspend mode,  
Data# Polling produces a 1on DQ[7]. If all sec-  
tors selected for erasing are protected, Data#  
Polling on DQ[7] is active for approximately 100  
μs, then the device returns to reading array data.  
If at least one selected sector is not protected, the  
erase operation erases the unprotected sectors,  
and ignores the command for the selected sec-  
tors that are protected.  
The HY29F002T provides a number of facilities to  
determine the status of a program or erase op-  
eration. These are provided through certain bits  
of a status word which can be read from the de-  
vice during the programming and erase operations.  
Table 6 summarizes the status indications and  
further detail is provided in the subsections which  
follow.  
DQ[7] - Data# Polling  
The Data# (Data Bar) Polling bit, DQ[7], indicates  
to the host system whether an Automatic Algo-  
rithm is in progress or completed, or whether the  
device is in Erase Suspend mode. Data# Polling  
is valid after the rising edge of the final WE# pulse  
in the Program or Erase command sequence.  
When the system detects that DQ[7] has changed  
from the complement to true data (or 0to 1for  
erase), it should do an additional read cycle to read  
valid data from DQ[7:0]. This is because DQ[7]  
may change asynchronously with respect to the  
other data bits while Output Enable (OE#) is as-  
serted low.  
The system must do a read at the program ad-  
dress to obtain valid programming status informa-  
tion on this bit. While a programming operation is  
in progress, the device outputs the complement  
of the value programmed to DQ[7]. When the pro-  
gramming operation is complete, the device out-  
puts the value programmed to DQ[7]. If a pro-  
gram operation is attempted within a protected  
sector, Data# Polling on DQ[7] is active for ap-  
proximately 2 μs, then the device returns to read-  
ing array data.  
Figure 7 illustrates the Data# Polling test algorithm.  
DQ[6] - Toggle Bit I  
Toggle Bit I on DQ[6] indicates whether an Auto-  
matic Program or Erase algorithm is in progress  
or complete, or whether the device has entered  
the Erase Suspend mode. Toggle Bit I may be  
read at any address, and is valid after the rising  
edge of the final WE# pulse in the program or erase  
command sequence, including during the sector  
erase time-out. The system may use either OE#  
or CE# to control the read cycles.  
The host must read at an address within any non-  
protected sector scheduled for erasure to obtain  
valid erase status information on DQ[7]. During  
Rev. 4.1/May 01  
15  
HY29F002T  
Successive read cycles at any address during an  
Automatic Program algorithm operation (including  
programming while in Erase Suspend mode)  
cause DQ[6] to toggle. DQ[6] stops toggling when  
the operation is complete. If a program address  
falls within a protected sector, DQ[6] toggles for  
approximately 2 μs after the program command  
sequence is written, then returns to reading array  
data.  
approximately 100 μs, then returns to reading ar-  
ray data. If at least one selected sector is not  
protected, the Automatic Erase algorithm erases  
the unprotected sectors, and ignores the selected  
sectors that are protected.  
DQ[2] - Toggle Bit II  
Toggle Bit II, DQ[2], when used with DQ[6], indi-  
cates whether a particular sector is actively eras-  
ing or whether that sector is erase-suspended.  
Toggle Bit II is valid after the rising edge of the  
final WE# pulse in the command sequence. The  
device toggles DQ[2] with each OE# or CE# read  
cycle.  
While the Automatic Erase algorithm is operating,  
successive read cycles at any address cause  
DQ[6] to toggle. DQ[6] stops toggling when the  
erase operation is complete or when the device is  
placed in the Erase Suspend mode. The host may  
use DQ[2] to determine which sectors are erasing  
or erase-suspended (see below). After an Erase  
command sequence is written, if all sectors se-  
lected for erasing are protected, DQ[6] toggles for  
DQ[2] toggles when the host reads at addresses  
within sectors that have been selected for erasure,  
but cannot distinguish whether the sector is ac-  
tively erasing or is erase-suspended. DQ[6], by  
comparison, indicates whether the device is ac-  
tively erasing or is in Erase Suspend, but cannot  
distinguish which sectors are selected for erasure.  
Thus, both status bits are required for sector and  
mode information.  
START  
Read DQ[7:0]  
at Valid Address (Note 1)  
Figure 8 illustrates the operation of Toggle Bits I  
and II.  
Test for DQ[7] = 1?  
for Erase Operation  
DQ[7] = Data?  
YES  
DQ[5] - Exceeded Timing Limits  
NO  
DQ[5] is set to a 1when the program or erase  
time has exceeded a specified internal pulse count  
limit. This is a failure condition that indicates that  
the program or erase cycle was not successfully  
completed. DQ[5] status is valid only while DQ[7]  
or DQ[6] indicate that an Automatic Algorithm is  
in progress.  
NO  
DQ[5] = 1?  
YES  
Read DQ[7:0]  
at Valid Address (Note 1)  
The DQ[5] failure condition will also be signaled if  
the host tries to program a 1to a location that is  
previously programmed to 0, since only an erase  
operation can change a 0to a 1.  
Test for DQ[7] = 1?  
for Erase Operation  
DQ[7] = Data?  
(Note 2)  
YES  
For both of these conditions, the host must issue  
a Read/Reset command to return the device to  
the Read mode.  
NO  
PROGRAM/ERASE  
EXCEEDED TIME ERROR  
PROGRAM/ERASE  
COMPLETE  
Notes:  
1. During programming, the program address.  
DQ[3] - Sector Erase Timer  
During sector erase, an address within any non-protected sector  
scheduled for erasure.  
During chip erase, an address within any non-protected sector.  
2. Recheck DQ[7] since it may change asynchronously at the same time  
as DQ[5].  
After writing a Sector Erase command sequence,  
the host may read DQ[3] to determine whether or  
not an erase operation has begun. When the  
sector erase time-out expires and the sector erase  
operation commences, DQ[3] switches from a 0’  
Figure 7. Data# Polling Test Algorithm  
Rev. 4.1/May 01  
16  
HY29F002T  
START  
DQ[5] = 1?  
YES  
Read DQ[7:0]  
at Valid Address (Note 1)  
NO  
Read DQ[7:0]  
Read DQ[7:0]  
Read DQ[7:0]  
at Valid Address (Note 1)  
Read DQ[7:0]  
at Valid Address (Note 1)  
YES  
NO  
DQ[6] Toggled?  
(Note 2)  
NO  
DQ[6] Toggled?  
DQ[2] Toggled?  
YES  
NO  
(Note 4)  
NO  
(Note 3)  
YES  
PROGRAM/ERASE  
COMPLETE  
PROGRAM/ERASE  
EXCEEDED TIME ERROR  
SECTOR BEING READ  
IS IN ERASE SUSPEND  
SECTOR BEING READ  
IS NOT IN ERASE SUSPEND  
Notes  
:
1. During programming, the program address.  
During sector erase, an address within any sector scheduled for erasure.  
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.  
3. Use this path if testing for Program/Erase status.  
4. Use this path to test whether sector is in Erase Suspend mode.  
Figure 8. Toggle Bit I and II Test Algorithm  
to a 1. Refer to the Sector Erase Command”  
section for additional information. Note that the  
sector erase timer does not apply to the Chip Erase  
command.  
all further sector erase data cycles or commands  
(other than Erase Suspend) are ignored until the  
erase operation is complete. If DQ[3] is a 0, the  
device will accept a sector erase data cycle to mark  
an additional sector for erasure. To ensure that  
the data cycles have been accepted, the system  
software should check the status of DQ[3] prior to  
and following each subsequent sector erase data  
cycle. If DQ[3] is high on the second status check,  
the last data cycle might not have been accepted.  
After the initial Sector Erase command sequence  
is issued, the system should read the status on  
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to  
ensure that the device has accepted the command  
sequence, and then read DQ[3]. If DQ[3] is a 1,  
the internally controlled erase cycle has begun and  
HARDWARE DATA PROTECTION  
Low VCC Write Inhibit  
The HY29F002T provides several methods of pro-  
tection to prevent accidental erasure or program-  
ming which might otherwise be caused by spuri-  
ous system level signals during VCC power-up and  
power-down transitions, or from system noise.  
These methods are described in the sections that  
follow.  
To protect data during VCC power-up and power-  
down, the device does not accept write cycles  
when VCC is less than VLKO (typically 3.7 volts). The  
command register and all internal program/erase  
circuits are disabled, and the device resets to the  
Read mode. Writes are ignored until VCC is greater  
than VLKO . The system must provide the proper  
signals to the control pins to prevent unintentional  
Command Sequences  
writes when VCC is greater than VLKO  
.
Commands that may alter array data require a  
sequence of cycles as described in Table 5. This  
provides data protection against inadvertent writes.  
Rev. 4.1/May 01  
17  
HY29F002T  
Write Pulse “Glitch” Protection  
Power-Up Write Inhibit  
Noise pulses of less than 5 ns (typical) on OE#,  
CE# or WE# do not initiate a write cycle.  
If WE# = CE# = VIL and OE# = VIH during power  
up, the device does not accept commands on the  
rising edge of WE#. The internal state machine is  
automatically reset to the Read mode on power-  
up.  
Logical Inhibit  
Write cycles are inhibited by asserting any one of  
the following conditions: OE# = VIL , CE# = VIH, or  
WE# = VIH. To initiate a write cycle, CE# and WE#  
must be a logical zero while OE# is a logical one.  
Sector Protection  
Additional data protection is provided by the  
HY29F002Ts sector protect feature, described  
previously, which can be used to protect sensitive  
areas of the Flash array from accidental or unau-  
thorized attempts to alter the data.  
Rev. 4.1/May 01  
18  
HY29F002T  
ABSOLUTE MAXIMUM RATINGS4  
Symbol  
Parameter  
Value  
Unit  
TSTG  
TBIAS  
Storage Temperature  
Ambient Temperature with Power Applied  
-65 to +150  
-55 to +125  
oC  
oC  
Voltage on Pin with Respect to VSS  
VCC1  
:
-2.0 to +7.0  
-2.0 to +12.5  
-2.0 to +7.0  
V
V
V
VIN2  
A[9], OE#, RESET# 2  
All Other Pins 1  
IOS  
Output Short Circuit Current 3  
200  
mA  
Notes:  
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to  
-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage  
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10.  
2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET#  
may undershoot VSS to 2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5  
V which may overshoot to 13.5 V for periods up to 20 ns.  
3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.  
4. Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a  
stress rating only; functional operation of the device at these or any other conditions above those indicated in the  
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for  
extended periods may affect device reliability.  
1
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Ambient Operating Temperature:  
Value  
Unit  
TA  
0 to +70  
oC  
Operating Supply Voltage:  
HY29F002-45 Versions  
All Other Versions  
VCC  
+4.75 to +5.25  
+4.50 to +5.50  
V
V
Notes:  
1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.  
20 ns  
20 ns  
20 ns  
VCC + 2.0 V  
0.8 V  
- 0.5 V  
VCC + 0.5 V  
2.0 V  
- 2.0 V  
20 ns  
20 ns  
20 ns  
Figure 9. Maximum Undershoot Waveform  
Figure 10. Maximum Overshoot Waveform  
Rev. 4.1/May 01  
19  
HY29F002T  
DC CHARACTERISTICS  
TTL/NMOS Compatible  
Parameter  
Description  
Test Setup  
Min  
Typ  
Max  
Unit  
VIN = VSS to VCC,  
VCC = VCC Max  
ILI  
Input Load Current  
±1.0  
μA  
VCC = VCC Max,  
A[9] = OE# = 12.5V  
RESET# = 12.5 V  
A[9], OE#, RESET# Input  
Load Current4  
ILIT  
50  
μA  
μA  
VOUT = VSS to VCC,  
VCC = VCC Max  
ILO  
ICC1  
ICC2  
ICC3  
Output Leakage Current  
±1.0  
VCC Active Read Current 1, 3  
VCC Active Write Current 2, 3, 4  
CE# = VIL, OE# = VIH  
CE# = VIL, OE# = VIH  
20  
30  
30  
40  
mA  
mA  
VCC CE# Controlled  
CE# = OE# = VIH  
RESET# = VIH  
0.4  
0.4  
1.0  
1.0  
mA  
mA  
TTL Standby Current 3  
VCC RESET# Controlled  
TTL Standby Current 3  
ICC4  
RESET# = VIL  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
-0.5  
2.0  
0.8  
V
V
VCC + 0.5  
Voltage for Electronic ID and  
Temporary Sector Unprotect  
VID  
VOL  
VOH  
V
CC = 5.0V  
11.5  
12.5  
0.45  
V
V
VCC = VCC Min,  
IOL = 12.0mA  
Output Low Voltage  
VCC = VCC Min,  
IOH = -2.5 mA  
Output High Voltage  
2.4  
3.2  
V
V
VLKO  
Low VCC Lockout Voltage 3  
4.2  
Notes:  
1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the  
CC current is typically less than 2 ma/MHz with OE# at VIH.  
I
2. ICC active while Automatic Erase or Automatic Program algorithm is in progress.  
3. ICC max measured with VCC = VCC max.  
4. Not 100% tested.  
Rev. 4.1/May 01  
20  
HY29F002T  
DC CHARACTERISTICS  
CMOS Compatible  
Parameter  
Description  
Test Setup  
Min  
Typ  
Max  
Unit  
VIN = VSS to VCC,  
VCC = VCC Max  
ILI  
Input Load Current  
±1.0  
μA  
μA  
μA  
VCC = VCC Max,  
A[9] = OE# = 12.5V  
RESET# = 12.5 V  
A[9], OE#, RESET# Input  
Load Current 4  
ILIT  
50  
VOUT = VSS to VCC,  
VCC = VCC Max  
ILO  
ICC1  
ICC2  
ICC3  
Output Leakage Current  
±1.0  
VCC Active Read Current 1, 3  
VCC Active Write Current 2, 3, 4  
CE# = VIL, OE# = VIH  
CE# = VIL, OE# = VIH  
20  
30  
30  
40  
mA  
mA  
VCC CE# Controlled  
CE# = VCC 0.5V  
RESET# = VCC 0.5V  
1
1
5
5
μA  
μA  
CMOS Standby Current 3  
VCC RESET# Controlled  
CMOS Standby Current 3  
ICC4  
RESET# = VSS 0.5V  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
-0.5  
0.8  
V
V
0.7 x VCC  
VCC + 0.3  
Voltage for Electronic ID and  
Temporary Sector Unprotect  
VID  
VCC = 5.0V  
11.5  
12.5  
0.45  
V
V
V
VCC = VCC Min,  
IOL = 12.0ma  
VOL  
Output Low Voltage  
VCC = VCC Min,  
IOH = -2.5 mA  
0.85 x  
VCC  
VOH  
Output High Voltage  
VCC = VCC Min,  
IOH = -100 μA  
VCC - 0.4  
3.2  
V
V
VLKO  
Low VCC Lockout Voltage 3  
4.2  
Notes:  
1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the  
CC current is typically less than 2 ma/MHz with OE# at VIH.  
I
2. ICC active while Automatic Erase or Automatic Program algorithm is in progress.  
3. ICC max measured with VCC = VCC max.  
4. Not 100% tested.  
KEY TO SWITCHING WAVEFORMS  
WAVEFORM  
INPUTS  
OUTPUTS  
Steady  
Changing from H to L  
Changing from L to H  
Don't Care, Any Change Permitted  
Does Not Apply  
Changing, State Unknown  
Centerline is High Impedance State  
(High Z)  
Rev. 4.1/May 01  
21  
HY29F002T  
TEST CONDITIONS  
+ 5V  
Table 7. Test Specifications  
Test  
Condition  
- 45 - 70  
- 55 - 90  
Unit  
2.7  
KOhm  
Output Load  
1 TTL Gate  
Output Load Capacitance (CL)  
Input Rise and Fall Times  
Input Signal Low Level  
Input Signal High Level  
30  
5
100  
20  
pF  
ns  
V
DEVICE  
UNDER  
TEST  
All diodes  
are  
1N3064  
or  
equivalent  
0.0  
3.0  
0.45  
2.4  
V
6.2  
KOhm  
CL  
Low Timing Measurement  
Signal Level  
1.5  
1.5  
0.8  
2.0  
V
V
High Timing Measurement  
Signal Level  
Figure 11. Test Setup  
3.0 V  
0.0 V  
I
nput  
1.5 V  
Measurement Level  
1.5 V  
Output  
HY29F002T-45, -55 Versions  
2.4 V  
2.0 V  
2.0 V  
0.8 V  
Measurement  
Input  
Output  
Levels  
0.8 V  
0.45 V  
HY29F002T-70, -90 Versions  
Figure 12. Input Waveforms and Measurement Levels  
Rev. 4.1/May 01  
22  
HY29F002T  
AC CHARACTERISTICS  
Read Operations  
Parameter  
Speed Option  
- 45 - 55 - 70 - 90  
Description  
Test Setup  
Unit  
JEDEC  
Std  
tAVAV  
tRC Read Cycle Time (Note 1)  
Min 45  
55  
70  
90  
ns  
ns  
CE# = VIL  
OE# = VIL  
tAVQV  
tACC Address to Output Delay  
Max 45  
55  
70  
90  
tELQV  
tEHQZ  
tGLQV  
tGHQZ  
tCE Chip Enable to Output Delay  
OE# = VIL Max 45  
Max 15  
55  
15  
25  
15  
70  
20  
30  
20  
90  
20  
35  
20  
ns  
ns  
ns  
ns  
ns  
tDF Chip Enable to Output High Z (Note 1)  
tOE Output Enable to Output Delay  
tDF Output Enable to Output High Z (Note 1)  
CE# = VIL Max 25  
Max 15  
Read  
Min  
0
Output Enable  
Hold Time (Note 1)  
tOEH  
Toggle and  
Data# Polling  
Min  
Min  
10  
ns  
ns  
Output Hold Time from Addresses, CE#  
or OE#, Whichever Occurs First (Note 1)  
tAXQX  
tOH  
0
Notes:  
1. Not 100% tested.  
2. See Figure 11 and Table 7 for test conditions.  
tRC  
Addresses  
CE#  
Addresses Stable  
tACC  
tOE  
OE#  
tOEH  
tDF  
WE#  
Outputs  
RESET#  
tCE  
tOH  
Output Valid  
Figure 13. Read Operation Timings  
Rev. 4.1/May 01  
23  
HY29F002T  
AC CHARACTERISTICS  
Hardware Reset (RESET#)  
Parameter  
Speed Option  
Description  
Test Setup  
Unit  
JEDEC  
Std  
- 45 - 55 - 70 - 90  
RESET# Pin Low (During Automatic  
tREADY Algorithms) to Read or Write (see Note  
1)  
Max  
Max  
20  
μs  
RESET# Pin Low (NOT During Automatic  
tREADY Algorithms) to Read or Write (see Note  
1)  
500  
ns  
tRP RESET# Pulse Width  
Min  
Min  
500  
50  
ns  
ns  
RESET# High Time Before Read (see  
tRH  
Note 1)  
Notes:  
1. Not 100% tested.  
2. See Figure 11 and Table 7 for test conditions.  
CE#, OE#  
RESET#  
tRH  
tRP  
tREADY  
Reset Timings NOT During Automatic Algorithms  
tREADY  
CE#, OE#  
RESET#  
tRP  
tRH  
Reset Timings During Automatic Algorithms  
Figure 14. RESET# Timings  
Rev. 4.1/May 01  
24  
HY29F002T  
AC CHARACTERISTICS  
Program and Erase Operations  
Parameter  
Speed Option  
- 45 - 55 - 70 - 90  
Description  
Unit  
JEDEC  
tAVAV  
Std  
tWC Write Cycle Time (Note 1)  
tAS Address Setup Time  
Min 45  
Min  
55  
70  
90  
ns  
ns  
tAVWL  
0
tWLAX  
tDVWH  
tWHDX  
tGHWL  
tELWL  
tAH Address Hold Time  
tDS Data Setup Time  
Min 40  
Min 25  
Min  
45  
25  
45  
30  
45  
45  
ns  
ns  
tDH Data Hold Time  
0
0
0
0
ns  
tGHWL Read Recovery Time Before Write  
tCS CE# Setup Time  
Min  
ns  
Min  
ns  
tWHEH  
tWLWH  
tWHWL  
tCH CE# Hold Time  
Min  
ns  
tWP Write Pulse Width  
tWPH Write Pulse Width High  
Min 30  
Min  
30  
35  
45  
ns  
20  
7
ns  
Typ  
μs  
tWHWH1 tWHWH1 Byte Programming Operation (Notes 1, 2, 3)  
Chip Programming Operation (Notes 1, 2, 3, 5)  
Max  
300  
1.8  
5.4  
1
μs  
Typ  
sec  
sec  
sec  
sec  
sec  
sec  
cycles  
cycles  
μs  
Max  
Typ  
tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2, 4)  
tWHWH3 tWHWH3 Chip Erase Operation (Notes 1, 2, 4)  
Max  
8
Typ  
7
Max  
55  
Typ  
1,000,000  
100,000  
50  
Erase and Program Cycle Endurance  
tVCS VCC Setup Time  
Min  
Min  
Notes:  
1. Not 100% tested.  
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 5.0 volts, 100,000 cycles. In addition,  
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-  
tions of 90 °C, VCC = 4.5 volts (4.75 volts for 45 ns version), 100,000 cycles.  
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program  
command. See Table 5 for further information on command sequences.  
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes  
are programmed to 0x00 before erasure.  
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most  
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum  
byte program time specified is exceeded. See Write Operation Status section for additional information.  
Rev. 4.1/May 01  
25  
HY29F002T  
AC CHARACTERISTICS  
Program Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
tW C  
tAS  
tAH  
Addresses  
CE#  
0x555  
PA  
PA  
PA  
tG H W L  
OE#  
tCH  
tW P  
WE#  
tCS  
tW P H  
tW H W H 1  
Data  
0xA0  
PD  
Status  
DOUT  
tDS  
tDH  
VCC  
tVCS  
Notes:  
1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address.  
2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.  
Figure 15. Program Operation Timings  
Rev. 4.1/May 01  
26  
HY29F002T  
AC CHARACTERISTICS  
Erase Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
tW C  
tAS  
tAH  
Addresses  
CE#  
0x2AA  
SA  
VA  
VA  
0x555 for chip erase  
tG H W L  
OE#  
tCH  
tW P  
WE#  
tW H W H 2 or tW H W H 3  
Status  
tCS  
tW P H  
0x10 for  
chip erase  
Data  
0x55  
0x30  
D OUT  
tDS  
tDH  
VCC  
tVCS  
Notes:  
1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),  
OUT is the true data at the read address.(0xFF after an erase operation).  
D
2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.  
Figure 16. Sector/Chip Erase Operation Timings  
Rev. 4.1/May 01  
27  
HY29F002T  
AC CHARACTERISTICS  
tRC  
VA  
Addresses  
VA  
VA  
tACC  
tCH  
tCE  
CE#  
tOE  
OE#  
WE#  
tDF  
tOEH  
tOH  
Complement  
Status Data  
Complement  
True  
Valid Data  
Valid Data  
DQ[7]  
Status Data  
True  
DQ[6:0]  
Notes:  
1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).  
2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.  
Figure 17. Data# Polling Timings (During Automatic Algorithms)  
tRC  
Addresses  
CE#  
VA  
VA  
VA  
VA  
tACC  
tCH  
tCE  
tOE  
OE#  
tDF  
tOEH  
WE#  
tOH  
Valid Status  
(first read)  
Valid Status  
(second read)  
Valid Status  
Valid Data  
DQ[6], [2]  
(stops toggling)  
Notes:  
1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section).  
2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.  
Figure 18. Toggle Polling Timings (During Automatic Algorithms)  
Rev. 4.1/May 01  
28  
HY29F002T  
AC CHARACTERISTICS  
Enter  
Automatic  
Erase  
Enter Erase  
Suspend  
Program  
Erase  
Suspend  
Erase  
Resume  
WE#  
Erase  
Erase  
Suspend  
Read  
Erase  
Suspend  
Program  
Erase  
Suspend  
Read  
Erase  
Erase  
Complete  
DQ[6]  
DQ[2]  
Notes:  
1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an  
erase-suspended sector.  
Figure 19. DQ[2] and DQ[6] Operation  
Sector Protect and Unprotect, Temporary Sector Unprotect  
Parameter  
JEDEC Std  
Speed Option  
- 45 - 55 - 70 - 90  
50  
Description  
Unit  
tST  
Voltage Setup Time  
Min  
Min  
μs  
μs  
RESET# Setup Time for  
Temporary Sector Group Unprotect  
tRSP  
4
tCE Chip Enable to Output Delay  
tOE Output Enable to Output Delay  
Max 45  
Max 25  
55  
25  
70  
30  
90  
35  
ns  
ns  
Voltage Transition Time for  
tVIDR  
Min  
Min  
500  
ns  
μs  
Temporary Sector Group Unprotect (Note 1)  
Voltage Transition Time for  
tVLHT  
4
Sector Group Protect and Unprotect (Note 1)  
tWPP1 Write Pulse Width for Sector Group Protect  
tWPP2 Write Pulse Width for Sector Group Unprotect  
tOESP OE# Setup Time to WE# Active (Note 1)  
tCSP CE# Setup Time to WE# Active (Note 1)  
Min  
Min  
Min  
Min  
100  
100  
4
μs  
ms  
μs  
μs  
4
Notes:  
1. Not 100% tested.  
Rev. 4.1/May 01  
29  
HY29F002T  
AC CHARACTERISTICS  
Sector Protect Cycle  
Protect Verify Cycle  
A[17:13]  
A[0]  
SA X  
SA Y  
A[1]  
A[6]  
tVLHT  
VID  
A[9]  
tVLHT  
tVLHT  
tST  
VID  
OE#  
tOESP  
tVLHT  
tWPP1  
tST  
WE#  
CE#  
tOE  
Data  
0x01  
RESET#  
tST  
tST  
VCC  
Figure 20. Sector Protect Timings  
Rev. 4.1/May 01  
30  
HY29F002T  
AC CHARACTERISTICS  
Sector Unprotect Cycle  
Unprotect Verify Cycle  
A[17:13]  
A[0]  
SA 0  
SA 1  
A[1]  
A[6]  
VID  
A[9]  
tST  
tVLHT  
tVLHT  
tST  
VID  
OE#  
CE#  
tOE  
tOESP  
VID  
tCE  
tCSP  
tWPP2  
WE#  
Data  
0x00  
RESET#  
VCC  
tST  
Figure 21. Sector Unprotect Timings  
Rev. 4.1/May 01  
31  
HY29F002T  
AC CHARACTERISTICS  
VID  
RESET#  
0 or 5V  
0 or 5V  
tVIDR  
tVIDR  
CE#  
WE#  
tRSP  
Figure 22. Temporary Sector Unprotect Timings  
Rev. 4.1/May 01  
32  
HY29F002T  
AC CHARACTERISTICS  
Alternate CE# Controlled Erase/Program Operations  
Parameter  
Speed Option  
- 45 - 55 - 70 - 90  
Description  
Unit  
JEDEC  
tAVAV  
Std  
tWC Write Cycle Time (Note 1)  
Min 45  
Min  
55  
70  
90  
ns  
ns  
tAVWL  
tWLAX  
tDVWH  
tWHDX  
tGHEL  
tWLEL  
tEHWH  
tELEH  
tAS  
Address Setup Time  
0
tAH Address Hold Time  
tDS Data Setup Time  
Min 40  
Min 25  
Min  
45  
25  
45  
30  
45  
45  
ns  
ns  
tDH Data Hold Time  
0
0
0
0
ns  
tGHEL Read Recovery Time Before Write  
tWS WE# Setup Time  
Min  
ns  
Min  
ns  
tWH WE# Hold Time  
Min  
ns  
tCP CE# Pulse Width  
Min 30  
Min  
30  
35  
45  
ns  
tEHEL  
tCPH CE# Pulse Width High  
20  
7
ns  
Typ  
μs  
tWHWH1 tWHWH1 Byte Programming Operation (Notes 1, 2, 3)  
Chip Programming Operation (Notes 1, 2, 3, 5)  
tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2, 4)  
tWHWH3 tWHWH3 Chip Erase Operation (Notes 1, 2, 4)  
Erase and Program Cycle Endurance  
Max  
300  
1.8  
5.4  
1
μs  
Typ  
sec  
sec  
sec  
sec  
sec  
sec  
cycles  
cycles  
Max  
Typ  
Max  
8
Typ  
7
Max  
55  
Typ  
1,000,000  
100,000  
Min  
Notes:  
1. Not 100% tested.  
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 5.0 volts, 100,000 cycles. In addition,  
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-  
tions of 90 °C, VCC = 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles.  
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program  
command. See Table 5 for further information on command sequences.  
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes  
are programmed to 0x00 before erasure.  
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most  
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum  
byte program time specified is exceeded. See Write Operation Status section for additional information.  
Rev. 4.1/May 01  
33  
HY29F002T  
AC CHARACTERISTICS  
PA for Program  
SA for Sector Erase  
0x555 for Chip Erase  
0x555 for Program  
0x2AA for Erase  
Addresses  
VA  
tW C  
tAS  
tAH  
WE#  
OE#  
CE#  
tGHEL  
tW H  
tCP  
tCPH  
tW H W H 1 or tW H W H 2 or tW H W H 3  
tW S  
tDS  
tDH  
Data  
Status  
DOUT  
0xA0 for Program  
0x55 for Erase  
PD for Program  
0x30 for Sector Erase  
0x10 for Chip Erase  
tRH  
RESET#  
Notes:  
1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write  
Operation Status section), DOUT = array data read at VA.  
2. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.  
3. Word mode addressing shown.  
4. RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command  
sequence.  
Figure 23. Alternate CE# Controlled Write Operation Timings  
Rev. 4.1/May 01  
34  
HY29F002T  
Latchup Characteristics  
Description  
Minimum  
Maximum  
Unit  
Input voltage with respect to VSS on all pins except I/O pins  
(including A[9], OE# and RESET#)  
-1.0  
12.5  
V
Input voltage with respect to VSS on all I/O pins  
- 1.0  
VCC + 1.0  
100  
V
VCC Current  
- 100  
mA  
Notes:  
1. Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.  
TSOP Pin Capacitance  
Symbol  
CIN  
Parameter  
Input Capacitance  
Test Setup  
VIN = 0  
Typ  
Max  
Unit  
pF  
6
7.5  
12  
9
COUT  
CIN2  
Output Capacitance  
VOUT = 0  
VIN = 0  
8.5  
7.5  
pF  
Control Pin Capacitance  
pF  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions: TA = 25 oC, f = 1.0 MHz.  
PLCC and PDIP Pin Capacitance  
Symbol  
CIN  
Parameter  
Input Capacitance  
Test Setup  
VIN = 0  
Typ  
4
Max  
6
Unit  
pF  
COUT  
CIN2  
Output Capacitance  
VOUT = 0  
VIN = 0  
8
12  
10  
pF  
Control Pin Capacitance  
8
pF  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions: TA = 25 oC, f = 1.0 MHz.  
Data Retention  
Parameter  
Test Conditions  
Minimum  
Unit  
Years  
Years  
150 oC  
125 oC  
10  
20  
Minimum Pattern Data Retention Time  
Rev. 4.1/May 01  
35  
HY29F002T  
PACKAGE DRAWINGS  
Physical Dimensions  
TSOP32 - 32-pin Thin Small Outline Package (measurements in millimeters)  
0.95  
1.05  
Pin 1 I.D.  
1
32  
17  
7.90  
8.10  
0.50 BSC  
16  
0.05  
0.15  
18.30  
18.50  
19.80  
20.20  
0.08  
0.20  
1.20  
MAX  
0.10  
0.21  
0o  
5o  
0.25MM (0.0098") BSC  
.015  
.060  
PLCC32 - 32-pin Plastic Leaded Chip Carrier (measurements in inches)  
.485  
.495  
.447  
.453  
.009  
.015  
Pin 1  
I.D.  
.042  
.056  
.585 .547  
.595  
.125  
.140  
.553  
.080  
.095  
SEATING  
PLANE  
.400  
REF  
.013  
.021  
.050 REF.  
.
026  
.490  
.530  
.032  
TOP VIEW  
SIDE VIEW  
Rev. 4.1/May 01  
36  
HY29F002T  
ORDERING INFORMATION  
Hynix products are available in several speeds, packages and operating temperature ranges. The  
ordering part number is formed by combining a number of fields, as indicated below. Refer to the Valid  
Combinationstable, which lists the configurations that are planned to be supported in volume. Please  
contact your local Hynix representative or distributor to confirm current availability of specific configura-  
tions and to determine if additional configurations have been released.  
HY29F002  
X
X
-
X
X
X
SPECIAL INSTRUCTIONS  
TEMPERATURE RANGE  
Blank = Commercial ( 0 to +70 °C)  
SPEED OPTION  
45 = 45 ns  
55 = 55 ns  
70 = 70 ns  
90 = 90 ns  
PACKAGE TYPE  
C = 32-Pin Plastic Leaded Chip Carrier (PLCC)  
T = 32-Pin Thin Small Outline Package (TSOP)  
BOOT BLOCK LOCATION  
T= Top Boot Block  
DEVICE NUMBER  
HY29F002 = 2 Megabit (256K x 8) CMOS 5 Volt-Only Sector  
Erase Flash Memory  
VALID COMBINATIONS  
Package and Speed  
TSOP  
PLCC  
70 ns  
C-70  
Temperature  
45 ns  
55 ns  
70 ns  
90 ns  
45 ns  
55 ns  
90 ns  
Commercial  
T-45  
T-55  
T-70  
T-90  
C-45  
C-55  
C-90  
Note:  
1. The complete part number is formed by appending the Boot Block Location code and the suffix shown in the table above  
to the Device Number. For example, the part number for a 90 ns, Commercial temperature range device in the TSOP  
package with the top boot block is HY29F002TT-90.  
Rev. 4.1/May 01  
37  
HY29F002T  
Important Notice  
? 2001 by Hynix Semiconductor America. All rights reserved.  
No part of this document may be copied or reproduced in any  
form or by any means without the prior written consent of Hynix  
Semiconductor Inc. or Hynix Semiconductor America (collec-  
tively Hynix).  
tions of Sale only. Hynix makes no warranty, express, statu-  
tory, implied or by description, regarding the information set  
forth herein or regarding the freedom of the described devices  
from intellectual property infringement. Hynix makes no war-  
ranty of merchantability or fitness for any purpose.  
The information in this document is subject to change without  
notice. Hynix shall not be responsible for any errors that may  
appear in this document and makes no commitment to update  
or keep current the information contained in this document.  
Hynix advises its customers to obtain the latest version of the  
device specification to verify, before placing orders, that the  
information being relied upon by the customer is current.  
Hynixs products are not authorized for use as critical compo-  
nents in life support devices or systems unless a specific writ-  
ten agreement pertaining to such intended use is executed  
between the customer and Hynix prior to use. Life support  
devices or systems are those which are intended for surgical  
implantation into the body, or which sustain life whose failure to  
perform, when properly used in accordance with instructions  
for use provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
Devices sold by Hynix are covered by warranty and patent in-  
demnification provisions appearing in Hynix Terms and Condi-  
Revision Record  
Rev. Date  
Details  
Change to Hynix format.  
Removed bottom boot block option and PDIP package option  
4.1  
5/01  
Memory Sales and Marketing Division  
Hynix Semiconductor Inc.  
10 Fl., Hynix Youngdong Building  
89, Daechi-dong  
Flash Memory Business Unit  
Hynix Semiconductor America Inc.  
3101 North First Street  
San Jose, CA 95134  
USA  
Kangnam-gu  
Seoul, Korea  
Telephone: (408) 232-8800  
Fax: (408) 232-8805  
Telephone: +82-2-580-5000  
Fax: +82-2-3459-3990  
http://www.us.hynix.com  
http://www.hynix.com  
Rev. 4.1/May 01  
38  
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